參數(shù)資料
型號(hào): LPC2119
廠商: NXP Semiconductors N.V.
英文描述: CLAMP
中文描述: 單片16/32位微控制器,128/256 kB ISP / IAP閃存的10位ADC和CAN
文件頁(yè)數(shù): 23/34頁(yè)
文件大?。?/td> 163K
代理商: LPC2119
Philips Semiconductors
LPC2119/LPC2129
Single-chip 16/32-bit microcontrollers
Product data
Rev. 03 — 22 December 2004
23 of 34
9397 750 13146
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.20.4
External interrupt inputs
The LPC2119/LPC2129 include up to nine edge or level sensitive External Interrupt
Inputs as selectable pin functions. When the pins are combined, external events can
be processed as four independent interrupt signals. The External Interrupt Inputs can
optionally be used to wake up the processor from Power-down mode.
6.20.5
Memory Mapping Control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x00000000. Vectors may be mapped to the bottom of the
on-chip Flash memory, or to the on-chip static RAM. This allows code running in
different memory spaces to have control of the interrupts.
6.20.6
Power Control
The LPC2119/LPC2129 support two reduced power modes: Idle mode and
Power-down mode. In Idle mode, execution of instructions is suspended until either a
Reset or interrupt occurs. Peripheral functions continue operation during Idle mode
and may generate interrupts to cause the processor to resume execution. Idle mode
eliminates power used by the processor itself, memory systems and related
controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal
clocks. The processor state and registers, peripheral registers, and internal SRAM
values are preserved throughout Power-down mode and the logic levels of chip
output pins remain static. The Power-down mode can be terminated and normal
operation resumed by either a Reset or certain specific interrupts that are able to
function without clocks. Since all dynamic operation of the chip is suspended,
Power-down mode reduces chip power consumption to nearly zero.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
6.20.7
VPB bus
The VPB divider determines the relationship between the processor clock (CCLK)
and the clock used by peripheral devices (PCLK). The VPB divider serves two
purposes. The first is to provide peripherals with the desired PCLK via VPB bus so
that they can operate at the speed chosen for the ARM processor. In order to achieve
this, the VPB bus may be slowed down to
1
2
to
1
4
of the processor clock rate.
Because the VPB bus must work properly at power-up (and its timing cannot be
altered if it does not work since the VPB divider control registers reside on the VPB
bus), the default condition at reset is for the VPB bus to run at
1
4
of the processor
clock rate. The second purpose of the VPB divider is to allow power savings when an
application does not require any peripherals to run at the full processor rate. Because
the VPB divider is connected to the PLL output, the PLL remains active (if it was
running) during Idle mode.
6.21 Emulation and debugging
The LPC2119/LPC2129 support emulation and debugging via a JTAG serial port. A
trace port allows tracing program execution. Debugging and trace functions are
multiplexed only with GPIOs on Port 1. This means that all communication, timer and
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