參數(shù)資料
型號(hào): LPC2119
廠商: NXP Semiconductors N.V.
英文描述: CLAMP
中文描述: 單片16/32位微控制器,128/256 kB ISP / IAP閃存的10位ADC和CAN
文件頁(yè)數(shù): 7/34頁(yè)
文件大?。?/td> 163K
代理商: LPC2119
Philips Semiconductors
LPC2119/LPC2129
Single-chip 16/32-bit microcontrollers
Product data
Rev. 03 — 22 December 2004
7 of 34
9397 750 13146
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P0.28
13
I
AIN1 —
A/D converter, input 1. This analog input is always connected to its
pin.
CAP0.2 —
Capture input for Timer 0, channel 2.
MAT0.2 —
Match output for Timer 0, channel 2.
AIN2 —
A/D converter, input 2. This analog input is always connected to its
pin.
CAP0.3 —
Capture input for Timer 0, Channel 3.
MAT0.3 —
Match output for Timer 0, channel 3.
AIN3 —
A/D converter, input 3. This analog input is always connected to its
pin.
EINT3 —
External interrupt 3 input.
CAP0.0 —
Capture input for Timer 0, channel 0.
Port 1:
Port 1 is a 32-bit bi-directional I/O port with individual direction
controls for each bit. The operation of port 1 pins depends upon the pin
function selected via the Pin Connect Block. Pins 0 through 15 of port 1 are
not available.
I
O
I
P0.29
14
I
O
I
P0.30
15
I
I
I/O
P1.0 to P1.31
16, 12, 8, 4,
48, 44, 40,
36, 32, 28,
24, 64, 60,
56, 52, 20
16
12
8
4
48
P1.16
P1.17
P1.18
P1.19
P1.20
O
O
O
O
O
TRACEPKT0 —
Trace Packet, bit 0. Standard I/O port with internal pull-up.
TRACEPKT1 —
Trace Packet, bit 1. Standard I/O port with internal pull-up.
TRACEPKT2 —
Trace Packet, bit 2. Standard I/O port with internal pull-up.
TRACEPKT3 —
Trace Packet, bit 3. Standard I/O port with internal pull-up.
TRACESYNC —
Trace Synchronization. Standard I/O port with internal
pull-up.
Note:
LOW on this pin while RESET is LOW, enables pins P1.25:16 to
operate as Trace port after reset.
PIPESTAT0 —
Pipeline Status, bit 0. Standard I/O port with internal pull-up.
PIPESTAT1 —
Pipeline Status, bit 1. Standard I/O port with internal pull-up.
PIPESTAT2 —
Pipeline Status, bit 2. Standard I/O port with internal pull-up.
TRACECLK —
Trace Clock. Standard I/O port with internal pull-up.
EXTIN0 —
External Trigger Input. Standard I/O with internal pull-up.
RTCK —
Returned Test Clock output. Extra signal added to the JTAG port.
Assists debugger synchronization when processor frequency varies.
Bi-directional pin with internal pull-up.
P1.21
P1.22
P1.23
P1.24
P1.25
P1.26
44
40
36
32
28
24
O
O
O
O
I
I/O
Note:
LOW on this pin while RESET is LOW, enables pins P1.31:26 to
operate as Debug port after reset.
TDO —
Test Data out for JTAG interface.
TDI —
Test Data in for JTAG interface.
TCK —
Test Clock for JTAG interface.
TMS —
Test Mode Select for JTAG interface.
TRST —
Test Reset for JTAG interface.
TD1 —
CAN1 transmitter output.
External Reset input:
A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0. TTL with hysteresis, 5 V tolerant.
P1.27
P1.28
P1.29
P1.30
P1.31
TD1
RESET
64
60
56
52
20
10
57
O
I
I
I
I
O
I
Table 3:
Symbol
Pin description
…continued
Pin
Type
Description
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