參數(shù)資料
型號(hào): LPC2210
廠商: NXP Semiconductors N.V.
英文描述: 16/32-bit ARM microcontroller with 10-bit ADC and external memory interface
中文描述: 與10位ADC和外部存儲(chǔ)器接口16/32位ARM微控制器
文件頁數(shù): 21/39頁
文件大?。?/td> 181K
代理商: LPC2210
Philips Semiconductors
LPC2210
16/32-bit ARM microcontrollers with external memory interface
Preliminary data
Rev. 01 — 09 February 2004
21 of 39
9397 750 12872
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
The I
2
C bus may be used for test and diagnostic purposes.
6.14 SPI serial I/O controller
The LPC2210 contains two SPIs. The SPI is a full duplex serial interface, designed to
be able to handle multiple masters and slaves connected to a given bus. Only a single
master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave,
and the slave always sends a byte of data to the master.
6.14.1
Features
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex, Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
6.15 General purpose timers
The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. It also includes four capture inputs to trap the timer value when an
input signal transitions, optionally generating an interrupt. Multiple pins can be
selected to perform a single capture or match function, providing an application with
‘or’ and ‘a(chǎn)nd’, as well as ‘broadcast’ functions among them.
6.15.1
Features
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Four 32-bit capture channels per timer that can take a snapshot of the timer value
when an input signal transitions. A capture event may also optionally generate an
interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Four external outputs per timer corresponding to match registers, with the following
capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.
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