參數(shù)資料
型號: LPC2292FET144/01,5
廠商: NXP Semiconductors
文件頁數(shù): 14/54頁
文件大?。?/td> 0K
描述: IC ARM7 MCU FLASH 256K 144TFBGA
標(biāo)準(zhǔn)包裝: 189
系列: LPC2200
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 60MHz
連通性: CAN,EBI/EMI,I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 112
程序存儲器容量: 256KB(256K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-TFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 705 (CN2011-ZH PDF)
配用: OM10091-ND - KIT DEV PHYCORE-ARM7/LPC2220
622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K
568-1757-ND - BOARD EVAL FOR LPC220X ARM MCU
其它名稱: 568-4320
935284897551
LPC2292FET144/01-S
LPC2292FET144/01-S-ND
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
21 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I2C-bus implemented in LPC2292/2294 supports bit rate up to 400 kbit/s (Fast
I2C-bus).
6.12.1 Features
Compliant with standard I2C-bus interface.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I2C-bus may be used for test and diagnostic purposes.
6.13 SPI serial I/O controller
The LPC2292/2294 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
6.13.1 Features
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex communication.
Combined SPI master and slave.
Maximum data bit rate of 18 of the input clock rate.
6.13.2 Features available in LPC2292/2294/01 only
Eight to 16 bits per frame.
When the SPI interface is used in Master mode, the SSELn pin is not needed (can be
used for a different function).
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