參數(shù)資料
型號(hào): LPC2292FET144/01,5
廠商: NXP Semiconductors
文件頁(yè)數(shù): 4/54頁(yè)
文件大?。?/td> 0K
描述: IC ARM7 MCU FLASH 256K 144TFBGA
標(biāo)準(zhǔn)包裝: 189
系列: LPC2200
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 60MHz
連通性: CAN,EBI/EMI,I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 112
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-TFBGA
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 705 (CN2011-ZH PDF)
配用: OM10091-ND - KIT DEV PHYCORE-ARM7/LPC2220
622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K
568-1757-ND - BOARD EVAL FOR LPC220X ARM MCU
其它名稱: 568-4320
935284897551
LPC2292FET144/01-S
LPC2292FET144/01-S-ND
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
12 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
P2[24]/D24
E2[7]
I/O
D24 — External memory data line 24.
P2[25]/D25
E1[7]
I/O
D25 — External memory data line 25.
P2[26]/D26/
BOOT0
I/O
D26 — External memory data line 26.
I
BOOT0 — While RESET is low, together with BOOT1
controls booting and internal operation. Internal pull-up
ensures high state if pin is left unconnected.
P2[27]/D27/
BOOT1
I/O
D27 — External memory data line 27.
I
BOOT1 — While RESET is low, together with BOOT0
controls booting and internal operation. Internal pull-up
ensures high state if pin is left unconnected.
BOOT1:0 = 00 selects 8-bit memory on CS0 for boot.
BOOT1:0 = 01 selects 16-bit memory on CS0 for boot.
BOOT1:0 = 10 selects 32-bit memory on CS0 for boot.
BOOT1:0 = 11 selects internal flash memory.
P2[28]/D28
I/O
D28 — External memory data line 28.
P2[29]/D29
I/O
D29 — External memory data line 29.
P2[30]/D30/
AIN4
I/O
D30 — External memory data line 30.
I
AIN4 — ADC, input 4. This analog input is always connected
to its pin.
P2[31]/D31/
AIN5
I/O
D31 — External memory data line 31.
I
AIN5 — ADC, input 5. This analog input is always connected
to its pin.
P3[0] to P3[31]
I/O
Port 3 — Port 3 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 3 pins
depends upon the pin function selected via the Pin Connect
Block.
P3[0]/A0
G12[7]
O
A0 — External memory address line 0.
P3[1]/A1
O
A1 — External memory address line 1.
P3[2]/A2
O
A2 — External memory address line 2.
P3[3]/A3
O
A3 — External memory address line 3.
P3[4]/A4
O
A4 — External memory address line 4.
P3[5]/A5
M13[7]
O
A5 — External memory address line 5.
P3[6]/A6
O
A6 — External memory address line 6.
P3[7]/A7
M12[7]
O
A7 — External memory address line 7.
P3[8]/A8
O
A8 — External memory address line 8.
P3[9]/A9
M10[7]
O
A9 — External memory address line 9.
P3[10]/A10
O
A10 — External memory address line 10.
P3[11]/A11
K9[7]
O
A11 — External memory address line 11.
P3[12]/A12
O
A12 — External memory address line 12.
P3[13]/A13
M9[7]
O
A13 — External memory address line 13.
P3[14]/A14
K7[7]
O
A14 — External memory address line 14.
P3[15]/A15
O
A15 — External memory address line 15.
P3[16]/A16
M7[7]
O
A16 — External memory address line 16.
Table 4.
Pin description …continued
Symbol
Pin (LQFP)
Pin
(TFBGA)[1]
Type
Description
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