參數(shù)資料
型號： LPC2294
廠商： NXP Semiconductors N.V.
英文描述： 16/32-bit ARM microcontrollers 256 kB ISP/IAP Flash with CAN, 10-bit ADC and external memory interface
中文描述： 16/32位ARM微控制器的256 KB的供應商/聯(lián)合會與CAN，10閃光位模數(shù)轉換器和外部存儲器接口
文件頁數(shù)： 7/40頁
文件大?。?/td> 188K
代理商： LPC2294
Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Preliminary data
Rev. 01 — 05 February 2004
7 of 40
9397 750 12748
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P0.27
23
I
AIN0 —
A/D converter, input 0. This analog input is always connected to its
pin.
CAP0.1 —
Capture input for Timer0, channel 1.
MAT0.1 —
Match output for Timer0, channel 1.
AIN1 —
A/D converter, input 1. This analog input is always connected to its
pin.
CAP0.2 —
Capture input for Timer0, channel 2.
MAT0.2 —
Match output for Timer0, channel 2.
AIN2 —
A/D converter, input 2. This analog input is always connected to its
pin.
CAP0.3 —
Capture input for Timer0, Channel 3.
MAT0.3 —
Match output for Timer0, channel 3.
AIN3 —
A/D converter, input 3. This analog input is always connected to its
pin.
EINT3 —
External interrupt 3 input.
CAP0.0 —
Capture input for Timer0, channel 0.
Port 1:
Port 1 is a 32-bit bi-directional I/O port with individual direction
controls for each bit. The operation of port 1 pins depends upon the pin
function selected via the Pin Connect Block.
Pins 2 through 15 of port 1 are not available.
I
O
I
P0.28
25
I
O
I
P0.29
32
I
O
I
P0.30
33
I
I
I/O
P1.0 to P1.31
91, 90, 34,
24, 15, 7,
102, 95, 86,
82, 70, 60,
52, 144, 140,
126, 113, 43
91
P1.0
O
CS0 —
Low-active Chip Select 0 signal.
(Bank 0 addresses range 8000 0000 - 80FF FFFF)
OE —
Low-active Output Enable signal.
TRACEPKT0 —
Trace Packet, bit 0. Standard I/O port with internal pull-up.
TRACEPKT1 —
Trace Packet, bit 1. Standard I/O port with internal pull-up.
TRACEPKT2 —
Trace Packet, bit 2. Standard I/O port with internal pull-up.
TRACEPKT3 —
Trace Packet, bit 3. Standard I/O port with internal pull-up.
TRACESYNC —
Trace Synchronization. Standard I/O port with internal
pull-up.
P1.1
P1.16
P1.17
P1.18
P1.19
P1.20
90
34
24
15
7
102
O
O
O
O
O
O
Note:
LOW on this pin while RESET is LOW, enables pins P1.25:16 to
operate as Trace port after reset.
PIPESTAT0 —
Pipeline Status, bit 0. Standard I/O port with internal pull-up.
PIPESTAT1 —
Pipeline Status, bit 1. Standard I/O port with internal pull-up.
PIPESTAT2 —
Pipeline Status, bit 2. Standard I/O port with internal pull-up.
TRACECLK —
Trace Clock. Standard I/O port with internal pull-up.
EXTIN0 —
External Trigger Input. Standard I/O with internal pull-up.
RTCK —
Returned Test Clock output. Extra signal added to the JTAG port.
Assists debugger synchronization when processor frequency varies.
Bi-directional pin with internal pull-up.
P1.21
P1.22
P1.23
P1.24
P1.25
P1.26
95
86
82
70
60
52
O
O
O
O
I
I/O
Note:
LOW on this pin while RESET is LOW, enables pins P1.31:26 to
operate as Debug port after reset.
TDO —
Test Data out for JTAG interface.
P1.27
144
O
Table 3:
Symbol
Pin description
…continued
Pin
Type
Description
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