參數(shù)資料
型號(hào)： LPC2294JBD144
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 16/32-bit ARM microcontrollers 256 kB ISP/IAP Flash with CAN, 10-bit ADC and external memory interface
中文描述： 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
文件頁(yè)數(shù)： 21/40頁(yè)
文件大?。?/td> 188K
代理商： LPC2294JBD144
Philips Semiconductors
LPC2292/LPC2294
16/32-bit ARM microcontrollers with external memory interface
Preliminary data
Rev. 01 — 05 February 2004
21 of 40
9397 750 12748
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
6.14 UARTs
The LPC2292/LPC2294 each contain two UARTs. One UART provides a full modem
control handshake interface, the other provides only transmit and receive data lines.
6.14.1
Features
16 byte Receive and Transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes
Built-in baud rate generator.
Standard modem interface signals included on UART1.
6.15 I
2
C serial I/O controller
I
2
C is a bi-directional bus for inter-IC control using only two wires: a serial clock line
(SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter
with the capability to both receive and send information (such as memory).
Transmitters and/or receivers can operate in either master or slave mode, depending
on whether the chip has to initiate a data transfer or is only addressed. I
2
C is a
multi-master bus, it can be controlled by more than one bus master connected to it.
I
2
C implemented in LPC2292/LPC2294 supports bit rate up to 400 kbit/s (Fast I
2
C).
6.15.1
Features
Standard I
2
C compliant bus interface.
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend
and resume serial transfer.
The I
2
C bus may be used for test and diagnostic purposes.
6.16 SPI serial I/O controller
The LPC2292/LPC2294 each contain two SPIs. The SPI is a full duplex serial
interface, designed to be able to handle multiple masters and slaves connected to a
given bus. Only a single master and a single slave can communicate on the interface
during a given data transfer. During a data transfer the master always sends a byte of
data to the slave, and the slave always sends a byte of data to the master.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LPC2294JBD144,551 功能描述:ARM微控制器 - MCU 256K FL/16K RM/4 CAN/ADC/EXT B RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
LPC2361 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Single-chip 16-bit/32-bit MCU; up to 128 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC
LPC2361_10 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Single-chip 16-bit/32-bit MCU; up to 128 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC
LPC2361FBD100 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Single-chip 16-bit/32-bit MCU; up to 128 kB flash with ISP/IAP, Ethernet, USB 2.0 device/host/OTG, CAN, and 10-bit ADC/DAC
LPC2361FBD100,551 功能描述:ARM微控制器 - MCU 64K FL/34K RAM USB OTG CAN RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
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