參數(shù)資料
型號： LPC2362FBD100
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學處理器
英文描述： Single-chip 16-bit-32-bit MCU; up to 128 kB flash with ISP-IAP, Ethernet, USB 2.0 device-host-OTG, CAN, and 10-bit ADC-DAC
封裝： LPC2361FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.html<1<Always Pb-free,;LPC2362FBD100<SOT407-1 (LQFP100)|<<http://www.nxp.com/packages/SOT407-1.htm
文件頁數(shù)： 55/64頁
文件大?。?/td> 475K
代理商： LPC2362FBD100
LPC2361_62
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 25 October 2011
55 of 64
NXP Semiconductors
LPC2361/62
Single-chip 16-bit/32-bit MCU
14.5 Standard I/O pin configuration
Figure 25
shows the possible pin modes for standard I/O pins with analog input function:
Digital output driver
Digital input: Pull-up enabled/disabled
Digital input: Pull-down enabled/disabled
Analog input (for ADC input channels)
The default configuration for standard I/O pins is input with pull-up enabled. The weak
MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.
Fig 25. Standard I/O pin configuration with analog input
PIN
V
DD
ESD
V
SS
ESD
V
DD
weak
pull-up
weak
pull-down
output enable
output
pull-up enable
pull-down enable
data input
analog input
select analog input
002aaf496
pin configured
as digital output
driver
pin configured
as digital input
pin configured
as analog input
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