參數(shù)資料
型號: LPC2919FBD144
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: ARM9 microcontroller with CAN and LIN
封裝: LPC2917FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LPC2919FBD144/01<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486
文件頁數(shù): 61/86頁
文件大?。?/td> 554K
代理商: LPC2919FBD144
LPC2917_19_01_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 9 December 2009
61 of 86
NXP Semiconductors
LPC2917/01; LPC2919/01
ARM9 microcontroller with CAN and LIN
[1]
All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T
amb
= 85
°
C on wafer
level. Cased products are tested at T
amb
= 25
°
C (final testing). Both pre-testing and final testing use correlated test conditions to cover
the specified temperature and power-supply voltage range.
[2]
Leakage current is exponential to temperature; worst-case value is at 85
°
C T
vj
. All clocks off. Analog modules and FLASH powered
down.
[3]
Not 5 V-tolerant when pull-up is on.
[4]
For I/O Port 0, the maximum input voltage is defined by V
I(ADC)
.
For Port 0, pin 0 to pin 15 add maximum 1.5 pF for input capacitance to ADC. For Port 0, pin 16 to pin 31 add maximum 1.0 pF for input
capacitance to ADC.
[5]
[6]
C
xtal
is crystal load capacitance and C
ext
are the two external load capacitors.
This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are
based on simulation results.
[7]
I
LIH
HIGH-level input leakage
current
LOW-level input leakage
current
pull-down input current
-
-
1
μ
A
I
LIL
-
-
1
μ
A
I
I(pd)
all port pins, V
I
= 3.3 V;
V
I
= 5.5 V; see
Figure 23
all port pins, RST, TRST,
TDI, JTAGSEL, TMS:
V
I
= 0 V; V
I
> 3.6 V is not
allowed; see
Figure 24
25
50
100
μ
A
I
I(pu)
pull-up input current
25
50
115
μ
A
C
i
Output pins and I/O pins configured as output
V
O
output voltage
V
OH
HIGH-level output voltage I
OH
=
4 mA
V
OL
LOW-level output voltage
C
L
load capacitance
Oscillator
V
XIN_OSC
voltage on pin XIN_OSC
R
s(xtal)
crystal series resistance
input capacitance
[5]
-
3
8
pF
0
V
DD(IO)
– 0.4
-
-
-
-
-
-
V
DD(IO)
-
0.4
25
V
V
V
pF
I
OL
= 4 mA
0
-
1.8
V
f
osc
= 10 MHz to 15 MHz
C
xtal
= 10 pF;
C
ext
= 18 pF
C
xtal
= 20 pF;
C
ext
= 39 pF
f
osc
= 15 MHz to 20 MHz
C
xtal
= 10 pF;
C
ext
= 18 pF
of XIN_OSC
[6]
-
-
160
Ω
-
-
60
Ω
[6]
-
-
80
Ω
C
i
Power-up reset
V
trip(high)
V
trip(low)
V
trip(dif)
input capacitance
[7]
-
2
pF
high trip level voltage
low trip level voltage
difference between high
and low trip level voltage
[8]
1.1
1.4
1.3
120
1.6
1.5
180
V
V
mV
[8]
1.0
[8]
50
Table 33.
V
DD(CORE)
= V
DD(OSC_PLL)
; V
DD(IO)
= 2.7 V to 3.6 V; V
DDA(ADC3V3)
= 3.0 V to 3.6 V; T
vj
= -40
°
C to +85
°
C; all voltages are
measured with respect to ground; positive currents flow into the IC; unless otherwise specified.
[1]
Symbol
Parameter
Conditions
Static characteristics
…continued
Min
Typ
Max
Unit
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