參數(shù)資料
型號: LPC2923FBD100
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: ARM9 microcontroller with CAN, LIN, and USB
中文描述: 32-BIT, FLASH, 125 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁數(shù): 27/84頁
文件大?。?/td> 551K
代理商: LPC2923FBD100
LPC2921_23_25_3
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 14 April 2010
27 of 84
NXP Semiconductors
LPC2921/2923/2925
ARM9 microcontroller with CAN, LIN, and USB
Internal loopback test mode.
The SPI module can operate in:
Master mode:
Normal transmission mode
Sequential slave mode
Slave mode
6.12.5.1
Functional description
The SPI module is a master or slave interface for synchronous serial communication with
peripheral devices that have either Motorola SPI or Texas Instruments Synchronous
Serial Interfaces.
The SPI module performs serial-to-parallel conversion on data received from a peripheral
device. The transmit and receive paths are buffered with FIFO memories
(16 bits wide
×
32 words deep). Serial data is transmitted on pins SDOx and received on
pins SDIx.
The SPI module includes a programmable bit-rate clock divider and prescaler to generate
the SPI serial clock from the input clock CLK_SPIx.
The SPI module’s operating mode, frame format, and word size are programmed through
the SLVn_SETTINGS registers.
A single combined interrupt request SPI_INTREQ output is asserted if any of the
interrupts are asserted and unmasked.
Depending on the operating mode selected, the SPI SCS outputs operate as an
active-HIGH frame synchronization output for Texas Instruments synchronous serial
frame format or an active-LOW chip select for SPI.
Each data frame is between four and 16 bits long, depending on the size of words
programmed, and is transmitted starting with the MSB.
6.12.5.2
Pin description
The SPI pins are combined with other functions on the port pins of the
LPC2921/2923/2925, see
Section 6.11.3
.
Table 15
shows the SPI pins (x runs from 0 to 2;
y runs from 0 to 3).
Table 15.
Symbol
SPIx SCSy
SPIx SCK
SPIx SDI
SPIx SDO
[1]
Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in
master mode, input in slave mode.
[2]
In slave mode there is only one chip select input pin, SPIx SCS0. The other chip selects have no function in
slave mode.
SPI pins
Pin name
SCSx[y]
SCKx
SDIx
SDOx
Direction
IN/OUT
IN/OUT
IN
OUT
Description
SPIx chip select
[1][2]
SPIx clock
[1]
SPIx data input
SPIx data output
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