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| 型號(hào)： | LPC47M14L-NC |
| 廠商： | SMSC Corporation |
| 英文描述： | EZ STIX CABLE INSTALLER STICKS |
| 中文描述： | 128引腳ENGANCED超級(jí)I / O與LPC接口和USB集線器控制器 |
| 文件頁(yè)數(shù)： | 115/205頁(yè) |
| 文件大?。?/td> | 1219K |
| 代理商： | LPC47M14L-NC |
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SMSC DS – LPC47M14X
Page 115
Rev. 03/19/2001
Miscellaneous Status Register (MSC_STS) is for the either edge triggered interrupt status bits. If the EETI function is
selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding MSC status bits.
Status bits are cleared on a write of ‘1’. See the “Runtime Registers” section for more information.
The configuration register for the either edge triggered interrupt status bits is defined in the “Runtime Registers”
section.
6.14.7
LED Functionality
The LPC47M14x provides LED functionality on two GPIOs, GP60 and GP61. These pins can be configured to turn
the LED on and off and blink independent of each other through the LED1 and LED2 runtime registers at offset 0x5D
and 0x5E from the base address located in the primary base I/O address in Logical Device A.
The LED pins (GP60 and GP61) are able to control the LED while the part is under VTR power with VCC removed.
In order to control an LED while the part is under VTR power, the GPIO pin must be configured for the LED function
and either open drain or push-pull buffer type. In the case of open-drain buffer type, the pin is capable of sinking
current to control the LED. In the case of push-pull buffer type, the part will source current. The part is also able to
blink the LED under VTR power, since the external 32kHz clock is always connected.
The LED pins can drive an LED when the buffer type is configured to be push-pull and the part is powered by either
VCC or VTR, since the buffers for these pins are powered by VTR. This means they will source their specified current
from VTR even when VCC is present.
The LED control registers are defined in the “Runtime Registers” section.
6.15 SYSTEM MANAGEMENT INTERRUPT (SMI)
The LPC47M14x implements a “group” nIO_SMI output pin. The System Management Interrupt is a non-maskable
interrupt with the highest priority level used for OS transparent power management. The nSMI group interrupt output
consists of the enabled interrupts from each of the functional blocks in the chip and many of the GPIOs and the Fan
tachometer pins. The GP27/nIO_SMI pin, when selected for the nIO_SMI function, can be programmed to be active
high or active low via the polarity bit in the GP27 register. The output buffer type of the pin can be programmed to be
open-drain or push-pull via bit 7 of the GP27 register. The nIO_SMI pin function defaults to active low, open-drain
output.
The interrupts are enabled onto the group nSMI output via the SMI Enable Registers 1 to 5. The nSMI output is then
enabled onto the group nIO_SMI output pin via bit[7] in the SMI Enable Register 2. The SMI output can also be
enabled onto the serial IRQ stream (IRQ2) via Bit[6] in the SMI Enable Register 2. The internal SMI can also be
enabled onto the nIO_PME pin. Bit[5] of the SMI Enable Register 2 is used to enable the SMI output onto the
nIO_PME pin (GP42). This bit will enable the internal SMI output into the PME logic through the DEVINT_STS bit in
PME_STS3. See PME section for more details.
An example logic equation for the nSMI output for SMI registers 1 and 2 is as follows:
nSMI = (EN_PINT and IRQ_PINT) or (EN_U2INT and IRQ_U2INT) or (EN_U1INT and IRQ_U1INT) or (EN_FINT and
IRQ_FINT) or (EN_MINT and IRQ_MINT) or (EN_KINT and IRQ_KINT) or (EN_IRINT and IRQ_IRINT)
6.15.1
SMI Registers
The SMI event bits for the GPIOs and the Fan tachometer events are located in the SMI status and Enable registers
3-5. The polarity of the edge used to set the status bit and generate an SMI is controlled by the polarity bit of the
control registers. For non-inverted polarity (default) the status bit is set on the low-to-high edge. If the EETI function
is selected for a GPIO then both a high-to-low and a low-to-high edge will set the corresponding SMI status bit.
Status bits for the GPIOs are cleared on a write of ‘1’.
The SMI logic for these events is implemented such that the output of the status bit for each event is combined with
the corresponding enable bit in order to generate an SMI.
The SMI registers are accessed at an offset from PME_BLK (see “Runtime Registers” section for more information).
The SMI event bits for the super I/O devices are located in the SMI status and enable register 1 and 2. All of these
status bits are cleared at the source except for IRINT, which is cleared by a read of the SMI_STS2 register; these
status bits are not cleared by a write of ‘1’. The SMI logic for these events is implemented such that each event is
directly combined with the corresponding enable bit in order to generate an SMI.
See the “Runtime Registers” section for the definition of these registers.
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