參數(shù)資料
型號(hào): LPC47M14Q-NC
廠商: SMSC Corporation
英文描述: HD VIEW RECEIVER 2 PORT DAISYCHAINABLE
中文描述: 128引腳ENGANCED超級(jí)I / O與LPC接口和USB集線器控制器
文件頁(yè)數(shù): 202/205頁(yè)
文件大?。?/td> 1219K
代理商: LPC47M14Q-NC
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)當(dāng)前第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)
SMSC DS – LPC47M14X
Page 202
Rev. 03/19/2001
Introduction
The LPC47M14x provides board test capability through the XNOR chain. When the chip is in the XNOR chain test
mode, setting the state of any of the input pins to the opposite of its current state will cause the output of the chain to
toggle.
All pins on the chip are inputs to the XNOR chain, with the exception of the following:
1)
VCC (pins 53, 65, 93, & 125), VTR (pins 18, 113, & 122), and VREF (pin 44).
2)
VSS (pins 7, 31, 60, 76, 101, 102, & 128) and AVSS (pin 40).
3)
TXD1 (pin 85) This is the chain output.
4)
nPCI_RESET (pin 26).
5)
OCLK (pin 124)
To put the chip in the XNOR chain test mode, tie LAD0 (pin 20) and LFRAME# (pin 24) low. Then toggle
PCI_RESET# (pin 26) from a low to a high state. Once the chip is put into XNOR chain test mode, LAD0 (pin 20) and
LFRAME# (pin 24) become part of the chain.
To exit the XNOR chain test mode tie LAD0 (pin 20) or LFRAME# (pin 24) high. Then toggle PCI_RESET# (pin 26)
from a low to a high state. A VCC POR will also cause the XNOR chain test mode to be exited. To verify the test
mode has been exited, observe the output at TXD1 (pin 85). Toggling any of the input pins should not cause its state
to change.
Setup
Warning:
Ensure power supply is off during setup.
Connect VSS (pins 7, 31, 60, 76, 101, 102, & 128) and AVSS (pin 40) to ground.
Connect VCC (pins 53, 65, 93, & 125), VTR (pins 18, 113, & 122), and VREF (pin 44)to VCC (3.3V).
Connect an oscilloscope or voltmeter to TXD1 (pin 85).
All other pins should be tied to ground.
1)
2)
3)
4)
Testing
1)
2)
Turn power on.
With LAD0 (pin 20) and LFRAME# (pin 24), low, bring PCI_RESET# (pin 26) high. The chip is now in XNOR
chain test mode. At this point, all inputs to the XNOR chain are low. The output, on TXD1 (pin 85), should
also be low. Refer to INITIAL CONFIG on Truth Table 1.
Bring pin 127 high. The output on TXD1 (pin 85) should go high. Refer to STEP ONE on Truth Table 1.
In descending pin order, bring each input high. The output should switch states each time an input is toggled.
Continue until all inputs are high. The output on TXD1 should now be low. Refer to END CONFIG on Truth
Table 1.
The current state of the chip is now represented by INITIAL CONFIG in Truth Table 2.
Each input should now be brought low, starting at pin one and continuing in ascending order. Continue until
all inputs are low. The output on TXD1 should now be low. Refer to Truth Table 2.
To exit test mode, tie LAD0 (pin 20) OR LFRAME# (pin 24) high, and toggle PCI_RESET# from a low to a
high state.
3)
4)
5)
6)
7)
相關(guān)PDF資料
PDF描述
LPC47M14V-NC AT PRINTER SERIAL CBL DB9 FEMALE - DB25 MALE
LPC47M14R-NC 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
LPC47M14I-NC 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
LPC47M14K-NC RESTR 1.50K 1 TOL 1/8W MF
LPC47M14P-NC 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LPC47M14R-NC 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
LPC47M14S-NC 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
LPC47M14T-NC 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
LPC47M14U-NC 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
LPC47M14V-NC 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB