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參數(shù)資料
| 型號： | LPC47M14Q-NC |
| 廠商： | SMSC Corporation |
| 英文描述： | HD VIEW RECEIVER 2 PORT DAISYCHAINABLE |
| 中文描述： | 128引腳ENGANCED超級I / O與LPC接口和USB集線器控制器 |
| 文件頁數(shù)： | 79/205頁 |
| 文件大?。?/td> | 1219K |
| 代理商： | LPC47M14Q-NC |
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SMSC DS – LPC47M14X
Page 79
Rev. 03/19/2001
Table 40 – Parallel Port Connector
HOST
CONNECTOR
PIN NUMBER
STANDARD
EPP
ECP
1
83
nStrobe
nWrite
nStrobe
2-9
68-75
PData<0:7>
PData<0:7>
PData<0:7>
10
80
nAck
Intr
nAck
11
79
Busy
nWait
Busy, PeriphAck(3)
12
78
PE
(User Defined)
PError,
nAckReverse (3)
13
77
Select
(User Defined)
Select
14
82
nAutoFd
nDatastb
nAutoFd,
HostAck(3)
15
81
nError
(User Defined)
nFault (1)
nPeriphRequest (3)
16
66
nInit
nRESET
nInit(1)
nReverseRqst(3)
17
67
nSelectIn
nAddrstrb
nSelectIn(1,3)
(1) = Compatible Mode
(3) = High Speed Mode
Note:
For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the
IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is
available from Microsoft.
6.9.1
IBM XT/AT Compatible, Bi-Directional and EPP Modes
DATA PORT
ADDRESS OFFSET = 00H
The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of
this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP mode,
PD0 - PD7 ports are buffered (not latched) and output to the host CPU.
STATUS PORT
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H' from the base address. The contents of this register are latched for the
duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O means
that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is cleared by a
RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration
Registers) is ‘0’, writing a one to this bit clears the TMOUT status bit. Writing a zero to this bit has no effect. If the
TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3 Configuration Registers) is
‘1’, the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register.
BITS 1, 2
- are not implemented as register bits, during a read of the Printer Status Register these bits are a low level.
BIT 3 nERR – nERROR
The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has
been detected; a logic 1 means no error has been detected.
BIT 4 SLCT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is on
line; a logic 0 means it is not selected.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LPC47M14R-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14S-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14T-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14U-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| LPC47M14V-NC | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
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