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參數(shù)資料
| 型號： | LPC47M14X |
| 廠商： | SMSC Corporation |
| 英文描述： | 128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB |
| 中文描述： | 128引腳ENGANCED超級I / O與LPC接口和USB集線器控制器 |
| 文件頁數(shù)： | 109/205頁 |
| 文件大?。?/td> | 1219K |
| 代理商： | LPC47M14X |
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SMSC DS – LPC47M14X
Page 109
Rev. 03/19/2001
6.13.10 Keyboard and Mouse PME Generation
The LPC47M14x sets the associated PME Status bits when the following conditions occur:
Keyboard Interrupt
Mouse Interrupt
Active Edge on Keyboard Data Signal (KDAT)
Active Edge on Mouse Data Signal (MDAT)
These events can cause a PME to be generated if the associated PME Wake Enable register bit and the global
PME_EN bit are set. Refer to the PME Support section for more details on the PME interface logic and refer to the
“Runtime Registers” section for details on the PME Status and Enable registers.
The keyboard interrupt and mouse interrupt PMEs can be generated when the part is powered by VCC. The
keyboard data and mouse data PMEs can be generated both when the part is powered by VCC, and when the part is
powered by VTR (VCC=0).
When using the keyboard and mouse data signals for wakeup, it may be necessary to isolate the keyboard signals
(KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep states. This is due to the fact that
the normal operation of the 8042 can prevent the system from entering a sleep state or trigger false PME events.
The LPC47M14x has “isolation” bits for the keyboard and mouse signals, which allow the keyboard and mouse data
signals to go into the wakeup logic but block the clock and data signals from the 8042. These bits may be used
anytime it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 before entering a system sleep
state.
See the SMSC Application Note titled “Keyboard and Mouse Wakeup Functionality” for more information.
The bits used to isolate the keyboard and mouse signals from the 8042 are located in Logical Device 7, Register
0xF0 (KRST_GA20) and are defined as follows:
Bit[6]
M_ISO. Enables/disables isolation of mouse signals into 8042. Does not affect the MDAT signal to
the mouse wakeup (PME) logic.
1=block mouse clock and data signals into 8042
0= do not block mouse clock and data signals into 8042
Bit[5]
K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT signal
to the keyboard wakeup (PME) logic.
1=block keyboard clock and data signals into 8042
0= do not block keyboard clock and data signals into 8042
When the keyboard and/or mouse isolation bits are used, it may be necessary to reset the 8042 upon exiting the
sleep state. If either of the isolation bits is set prior to entering a sleep state where VCC goes inactive (S3-S5), then
the 8042 must be reset upon exiting the sleep mode. Write 0x40 to global configuration register 0x2C to reset the
8042. The 8042 must then be taken out of reset by writing 0x00 to register 0x2C since the bit that resets the 8042 is
not self-clearing. Caution: Bit 6 of configuration register 0x2C is used to put the 8042 into reset - do not set any of the
other bits in register 0x2C, as this may produce undesired results.
It is not necessary to reset the 8042 if the isolation bits are used for a sleep state where VCC does not go inactive
(S1, S2).
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