SMSC DS – LPC47M192
Page 114
Rev. 03/30/05
DATASHEET
GPIO PIN
GPIO REGISTER
PIN#
PIN NAME
(Default Func/
Alternate Funcs)
PWR
WELL
PCI
RESET
VCC
POR
VTR
POR
REG
OFFS
ET
(hex)
3E
REG
PCI
RESET
VCC
POR
VTR
POR
SOFT
RESET
SMI/PME
NOTES
28
GP43/DDRC
VCC
In
In
In
GP43
Note 5
Note
5
-
-
-
0x00
0x01
-
SMI/PME
1, 5
92
94
95
96
GP50/nRI2
GP51/nDCD2
GP52/RXD2(IRRX)
GP53/TXD2 (IRTX)
VCC
VCC
VCC
VTR
-
-
-
-
-
-
In
In
In
3F
40
41
42
GP50
GP51
GP52
GP53
-
-
-
0x01
0x01
0x01
0x00
-
-
-
-
PME
PME
PME
PME
1
1
1
Out – low
Out–
low
-
-
-
-
-
-
Out–
low
In
In
In
In
In
In
0x00
1, 3
97
98
99
100
48
49
GP54/nDSR2
GP55/nRTS2
GP56/nCTS2
GP57/nDTR2
GP60/LED1
GP61/LED2
VCC
VCC
VCC
VCC
VTR
VTR
-
-
-
-
-
-
43
44
45
46
47
48
GP54
GP55
GP56
GP57
GP60
GP61
-
-
-
-
-
-
-
-
-
-
-
-
0x01
0x01
0x01
0x01
0x01
0x01
-
-
-
-
-
-
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
SMI/PME
1
1
1
1
1
1
Note 1:
These pins are inputs to VCC and VTR powered logic.
Note 2:
The fan control pins (FAN1 and FAN2) come up as outputs and low following a VCC POR and PCI Reset.
Note 3:
The IRTX pins (IRTX2/GP35 and GP53/TXD2(IRTX)) are driven low when the part is powered by VTR
(VCC=0V with VTR=3.3V). These pins will remain low following a VCC POR until IRTX function is selected
by setting the activate bit, at which time the pin will reflect the state of the transmit output of the IR block. It
will remain low following a VCC POR until GPIO input function is selected, at which time the pin will reflect
the state of the GPIO data bit. The GP53/TXD2 (IRTX) pin will remain low following a VCC POR (in
addition to conditions stated above) until serial port 2 is enabled by setting the activate bit, at which time
the pin will reflect the state of the transmit output of the Serial Port 2 block.
Note 4:
These pins are inputs to VCC powered logic.
Note 5:
Bits [3:2] (Alternate Function Select bits) of this register are reset (cleared) on VCC POR and PCI Reset
(and VTR POR).
7.12.2 DESCRIPTION
Each GPIO port has a 1-bit data register and an 8-bit configuration control register. The data register for each GPIO
port is represented as a bit in one of the 8-bit GPIO DATA Registers, GP1 to GP6. The bits in these registers reflect
the value of the associated GPIO pin as follows. Pin is an input: The bit is the value of the GPIO pin. Pin is an
output: The value written to the bit goes to the GPIO pin. Latched on read and write. All of the GPIO registers are
located in the PME block see “Run Time Register” section. The GPIO ports with their alternate functions and
configuration state register addresses are listed in Table 53.
Table 53 - General Purpose I/O Port Assignments
QFP
PIN#
DEFAULT
FUNCTION
ALT. FUNC. 1
ALT.
FUNC. 2
ALT.
FUNC. 3
DATA
REGISTER
1
DATA
REGISTER
BIT NO.
0
1
2
3
4
5
6
7
0
1
2
3
4
REGISTER
OFFSET
(HEX)
4B
32
33
34
35
36
37
38
39
41
42
43
N/A
45
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Reserved
GPIO
(System
Option)
GPIO
GPIO
Joystick 1 Button 1
Joystick 1 Button 2
Joystick 2 Button 1
Joystick 2 Button 2
Joystick 1 X-Axis
Joystick 1 Y-Axis
Joystick 2 X-Axis
Joystick 2 Y-Axis
P17
P16
P12
GP1
EETI
EETI
46
47
MIDI_IN
MIDI_OUT
5
6
GP2
4C