73
SERIAL PORT (UART)
The LPC47S42x incorporates two full function UARTs. They are compatible with the NS16450, the 16450
ACE registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received
characters and parallel-to-serial conversion on transmit characters. The data rates are independently
programmable from 460.8K baud down to 50 baud. The character options are programmable for 1 start;
1, 1.5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. The UARTs each contain a
programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1
to 65535. The UARTs are also capable of supporting the MIDI data rate. Refer to the Configuration
Registers for information on disabling, power down and changing the base address of the UARTs. The
interrupt from a UART is enabled by programming OUT2 of that UART to a logic "1". OUT2 being a logic
"0" disables that UART's interrupt. The second UART also supports IrDA 1.0, HP-SIR, ASK-IR infrared
modes of operation.
Note: The UARTs 1 and 2 may be configured to share an interrupt. Refer to the Configuration section for
more information.
Register Description
Addressing of the accessible registers of the Serial Port is shown below. The base addresses of the serial
ports are defined by the configuration registers (see Configuration section). The Serial Port registers are
located at sequentially increasing addresses above these base addresses. The LPC47S42x contains two
serial ports, each of which contain a register set as described below.
Table 28 - Addressing the Serial Port
DLAB*
A2
A1
A0
0
0
0
0
Receive Buffer (read)
0
0
0
0
Transmit Buffer (write)
0
0
0
1
Interrupt Enable (read/write)
X
0
1
0
Interrupt Identification (read)
X
0
1
0
FIFO Control (write)
X
0
1
1
Line Control (read/write)
X
1
0
0
Modem Control (read/write)
X
1
0
1
Line Status (read/write)
X
1
1
0
Modem Status (read/write)
X
1
1
1
Scratchpad (read/write)
1
0
0
0
Divisor LSB (read/write)
1
0
0
1
Divisor MSB (read/write
*Note: DLAB is Bit 7 of the Line Control Register
The following section describes the operation of the registers.
Receive Buffer Register (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted
and received first. Received data is double buffered; this uses an additional shift register to receive the
serial data stream and convert it to a parallel 8 bit word which is transferred to the Receive Buffer register.
The shift register is not accessible.
REGISTER NAME