參數(shù)資料
型號(hào): LPC47S422-MS
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 外設(shè)及接口
英文描述: ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS
中文描述: MULTIFUNCTION PERIPHERAL, PQFP100
封裝: LEAD FREE, QFP-100
文件頁數(shù): 92/264頁
文件大?。?/td> 1342K
代理商: LPC47S422-MS
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁當(dāng)前第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁
The Data Port is located at an offset of '00H' from the base address. The data register is cleared at
initialization by RESET. During a WRITE operation, the Data Register latches the contents of the internal
data bus. The contents of this register are buffered (non inverting) and output onto the PD0 - PD7 ports.
During a READ operation in SPP mode, PD0 - PD7 ports are buffered (not latched) and output to the host
CPU.
Status Port
ADDRESS OFFSET = 01H
The Status Port is located at an offset of '01H' from the base address. The contents of this register are
latched for the duration of a read cycle. The bits of the Status Port are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A
logic O means that no time out error has occurred; a logic 1 means that a time out error has been
detected. This bit is cleared by a RESET. Writing a one to this bit clears the time out status bit. On a
write, this bit is self clearing and does not require a write of a zero. Writing a zero to this bit has no effect.
BITS 1, 2
- are not implemented as register bits, during a read of the Printer Status Register these bits are
a low level.
BIT 3 nERR - nERROR
The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0
means an error has been detected; a logic 1 means no error has been detected.
BIT 4 SLCT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means
the printer is on line; a logic 0 means it is not selected.
BIT 5 PE - PAPER END
The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a
paper end; a logic 0 indicates the presence of paper.
BIT 6 nACK - nACKNOWLEDGE
The level on the nACK input is read by the CPU as bit 6 of the Printer Status Register. A logic 0 means
that the printer has received a character and can now accept another. A logic 1 means that it is still
processing the last character or has not received the data.
BIT 7 nBUSY - nBUSY
The complement of the level on the BUSY input is read by the CPU as bit 7 of the Printer Status Register.
A logic 0 in this bit means that the printer is busy and cannot accept a new character. A logic 1 means that
it is ready to accept the next character.
Control Port
ADDRESS OFFSET = 02H
The Control Port is located at an offset of '02H' from the base address. The Control Register is initialized
by the RESET input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low.
92
相關(guān)PDF資料
PDF描述
LPC47S422QFP ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS
LPC47U33x 100 Pin Enhanced Super I/O for LPC Bus with Consumer Features and SMBus Controller
LPC870-FJ Mini SIDELED
LPC870-G Mini SIDELED
LPC870-GK Mini SIDELED
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LPC47S422QFP 制造商:Rochester Electronics LLC 功能描述:SUPER 1/O CONTROLLER W/LPC - Bulk
LPC47S42X 制造商:SMSC 制造商全稱:SMSC 功能描述:ENHANCED SUPER I/O WITH LPC INTERFACE FOR SERVER APPLICATIONS
LPC47S457-NC 功能描述:輸入/輸出控制器接口集成電路 Enhanced Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
LPC47S457-NS 功能描述:接口 - 專用 Enhanced Super I/O Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
LPC47S45X 制造商:SMSC 制造商全稱:SMSC 功能描述:Advanced I/O with X-Bus Interface