LRS1382
5
3. Truth Table
3.1 Bus Operation
(1)
Notes:
1. L = V
IL
, H = V
IH
, X = H or L, High-Z = High impedance. Refer to the DC Characteristics.
2. Command writes involving block erase, (page buffer) program are reliably executed when F-V
PP
= V
PPH1/2
and F-V
CC
= 2.7V to 3.3
V
.
Command writes involving full chip erase is reliably executed when F-V
PP
= V
PPH1
and F-V
CC
= 2.7V to 3.3
V
.
Block erase, full chip erase, (page buffer) program with F-V
PP
< V
PPH1/2
(Min.) produce spurious results and should not
be attempted.
3. Never hold F-OE low and F-WE low at the same timing.
4. Refer to Section 5. Command Definitions for Flash Memory valid D
IN
during a write operation.
5. F-WP set to V
IL
or
V
IH
.
6. Electricity consumption of Flash Memory is lowest when F-RST = GND ±0.2V.
7. Flash Read Mode
8. SRAM Standby Mode
S-CE
1
S-CE
2
9. S-UB, S-LB Control Mode
S-LB
S-UB
Flash
SRAM
Notes
F-CE
F-RST F-OE F-WE S-CE
1
S-CE
2
S-OE S-WE S-LB S-UB DQ
0
to DQ
15
L
H
(8)
X
H
L
Read
Output
Disable
Standby
3,5
L
H
X
(8)
(7)
5
High-Z
Write
2,3,4,5
D
IN
Standby
Read
5
H
H
X
X
L
H
L
H
(9)
Output
Disable
5
H
X
X
H
X
L
X
H
X
H
High-Z
Write
5
(9)
Reset Power
Down
Read
5,6
X
L
X
X
L
H
L
H
X
H
H
X
(9)
Output
Disable
5,6
X
H
X
H
High-Z
Write
5,6
5
X
L
(9)
Standby
Reset Power
Down
Standby
H
H
X
X
(8)
X
X
(8)
High-Z
5,6
X
L
Mode
Address
DQ
0
to DQ
15
Read Array
X
D
OUT
Read Identifier Codes
See 5.2
See 5.2
Read Query
Refer to the Appendix
Refer to the Appendix
S-LB
S-UB
DQ
0
to DQ
7
D
OUT
/D
IN
D
OUT
/D
IN
DQ
8
to DQ
15
D
OUT
/D
IN
H
X
X
X
L
L
X
L
X
X
L
H
High-Z
X
X
H
H
H
L
High-Z
D
OUT
/D
IN