參數(shù)資料
型號: LRS1360C
英文描述: MIXED MEMORY|SRAM+EEPROM|HYBRID|BGA|72PIN|PLASTIC
中文描述: 混合存儲器|靜態(tài)存儲器EEPROM中|混合|的BGA | 72PIN |塑料
文件頁數(shù): 6/43頁
文件大?。?/td> 1326K
代理商: LRS1360C
LRS1382
4
Pin
Description
Type
A
0
to A
16
, A
18
F-A
17
,
F-A
19
, F-A
20
S-A
17
F-CE
S-CE
1
, S-CE
2
F-WE
S-WE
F-OE
Address Inputs (Common)
Input
Address Inputs (Flash)
Input
Address Input (SRAM)
Input
Chip Enable Input (Flash)
Input
Chip Enable Inputs (SRAM)
Input
Write Enable Input (Flash)
Write Enable Input (SRAM)
Output Enable Input (Flash)
Input
Input
Input
S-OE
Output Enable Input (SRAM)
SRAM Byte Enable Input (DQ
0
to DQ
7
)
SRAM Byte Enable Input (DQ
8
to DQ
15
)
Reset Power Down Input (Flash)
Block erase and Write : V
IH
Read : V
IH
Reset Power Down : V
IL
Write Protect Input (Flash)
When F-WP is V
IL
, locked-down blocks cannot be unlocked. Erase or
program operation can be executed to the blocks which are not locked and
locked-down. When F-WP is V
IH
, lock-down is disabled.
Ready/Busy Output (Flash)
During an Erase or Write operation : V
OL
Block Erase and Write Suspend : High-Z (High impedance)
Input
S-LB
Input
S-UB
Input
F-RST
Input
F-WP
Input
F-RY/BY
Open Drain
Output
DQ
0
to DQ
15
F-V
CC
S-V
CC
Data Inputs and Outputs (Common)
Input / Output
Power Supply (Flash)
Power
Power Supply (SRAM)
Power
F-V
PP
Monitoring Power Supply Voltage (Flash)
Block Erase and Write : F-V
PP
= V
PPH1/2
All Blocks Locked : F-V
PP
< V
PPLK
GND (Common)
Input
GND
Power
NC
Non Connection
-
T
1
to T
3
Test pins (Should be all open)
-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LRS1361B 制造商:Sharp Microelectronics 功能描述:QUOTE B04419SC
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LRS1380J 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:STACKED CHIP 32M (X 16) BOOT BLOCK FLASH AND 4M (X 16) SRAM