參數(shù)資料
型號： LS4301-7R
英文描述： 100 Watt AC-DC Converters with PFC
中文描述： 100瓦交直流轉(zhuǎn)換器的功率因數(shù)校正
文件頁數(shù)： 25/27頁
文件大?。?/td> 599K
代理商： LS4301-7R
Cassette Style
100 Watt AC-DC Converters
S Series PFC
Edition 01/01.2001
25/27
V ACFAIL Signal (VME)
Available for units with U
o1
= 5.1V
This option de
fi
nes an undervoltage monitoring circuit for
the input or input and main output voltage equivalent to op-
tion D and generates the ACFAIL signal (V signal) which
conforms to the VME standard.
The low state level of the ACFAIL signal is speci
fi
ed at a
sink current of I
V
≤
48 mA to U
V
≤
0.6 V (open-collector out-
put of a NPN transistor). The pull-up resistor feeding the
open-collector output should be placed on the VME back
plane.
After the ACFAIL signal has gone low, the VME standard
requires a hold-up time t
h
of at least 4 ms before the 5.1 V
output drops to 4.875 V when the output is fully loaded.
This hold-up time t
h
is provided by the internal input capaci-
tance. See also
fi
g.: Hold-up Time versus Output Power
Table 20: Undervoltage monitor functions
V output
Monitoring
U
i
Minimum adjustment
range of threshold level
U
ti
(VME compatible)
U
o1
U
to
V2
yes
no
355V DC
1
–
V3
yes
yes
355V DC
1
0.95...0.985 U
o1 2
1
Option D monitors the boost regulator output voltage. The trig-
ger level is adjusted in the factory to 355 V DC.
2
Fixed value between 95% and 98.5% of U
o1
.
Vo1+
Vo1
–
V
U
V
I
V
R
p
I
11009
V output (V2, V3):
Connector pin V is internally connected to the open collec-
tor of a NPN transistor. The emitter is connected to the
negative potential of output 1. U
V
≤
0.6 V (logic low) corre-
sponds to a monitored voltage level (U
i
and/or U
o1
)
<
U
t
.
The current I
V
through the open collector should not ex-
ceed 50 mA. The NPN output is not protected against ex-
ternal overvoltages. U
V
should not exceed 60 V.
U
i
, U
o1
status
U
i
or U
o1
<
U
t
U
i
and U
o1
>
U
t
+ U
h
V output, U
V
low, L, U
V
≤
0.6 V at I
V
= 50 mA
high, H, I
V
≤
25
μ
A at U
V
= 5.1 V
Fig. 39
Output con
fi
guration of options V2 and V3
Option V operates independently of the built-in input under-
voltage lock-out circuit. A logic "low" signal is generated at
pin 20 as soon as one of the monitored voltages drops be-
low the preselected threshold level U
t
. The return for this
signal is Vo1
–
. The V output recovers when the monitored
voltage(s) exceed(s) U
t
+ U
h
. The threshold level U
ti
is ad-
justed in the factory to 355 V DC. The threshold level U
to
either is adjusted during manufacture to a determined cus-
tomer speci
fi
ed value.
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