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參數(shù)資料
| 型號(hào)： | lS80C86 |
| 廠商： | Intersil Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | CMOS 16-Bit Microprocessor |
| 中文描述： | 的CMOS 16位微處理器 |
| 文件頁(yè)數(shù)： | 23/35頁(yè) |
| 文件大?。?/td> | 339K |
| 代理商： | LS80C86 |
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3-163
(35)
TCVNV
Control Active Delay (Note 10)
5
45
5
45
ns
C
L
= 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(36)
TCVNX
Control Inactive Delay (Note 10)
10
45
10
45
ns
C
L
= 100pF
(37)
TAZRL
Address Float to Read Active
0
0
ns
C
L
= 100pF
(38)
TCLRL
RD Active Delay
10
165
10
100
ns
C
L
= 100pF
(39)
TCLRH
RD Inactive Delay
10
150
10
80
ns
C
L
= 100pF
(40)
TRHAV
RD Inactive to Next Address Active
TCLCL
-45
TCLCL
-40
ns
C
L
= 100pF
(41)
TCHDTL
Direction Control Active Delay
(Note 10)
50
50
ns
C
L
= 100pF
(42)
TCHDTH
Direction Control Inactive Delay
(Note 10)
30
30
ns
C
L
= 100pF
(43)
TCLGL
GT Active Delay
10
85
0
50
ns
C
L
= 100pF
(44)
TCLGH
GT Inactive Delay
10
85
0
50
ns
C
L
= 100pF
(45)
TRLRH
RD Width
2TCLC
L -75
2TCLC
L -50
ns
C
L
= 100pF
(46)
TOLOH
Output Rise Time
20
15
ns
From 0.8V to 2.0V
(47)
TOHOL
Output Fall Time
20
15
ns
From 2.0V to 0.8V
NOTES:
10. Signal at 82C84A or 82C88 shown for reference only.
11. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
12. Applies only to T2 state (8ns into T3).
13. The 80C86 actively pulls the RQ/GT pin to a logic one on the following clock low time.
14. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
AC Electrical Specifications
V
CC
= 5.0V
±
10%
V
CC
= 5.0V
±
10%; T
A
= -40
o
C to +85
o
C (I80C86, I80C86-2)
V
CC
= 5.0V
±
10%; T
A
= -55
o
C to +125
o
C (M80C86)
V
CC
= 5.0V
±
5%;
T
A
= 0
o
C to +70
o
C (C80C86, C80C86-2)
T
A
= -55
o
C to +125
o
C (M80C86-2)
(Continued)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING REQUIREMENTS
80C86
80C86-2
UNITS
TEST CONDITIONS
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
80C86
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| LS80C88 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8/16-Bit Microprocessor |
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