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參數(shù)資料
| 型號： | lS80C88 |
| 廠商： | Intersil Corporation |
| 元件分類： | 16位微控制器 |
| 英文描述： | CMOS 8/16-Bit Microprocessor |
| 中文描述： | 16位產(chǎn)品的CMOS微處理器 |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 246K |
| 代理商： | LS80C88 |
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3-4
Pin Description
The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “l(fā)ocal bus” in these
descriptions is the direct multiplexed bus interface connection to the 80C88 (without regard to additional bus buffers).
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
AD7-AD0
9-16
I/O
ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and
data (T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last
valid level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”
A15-A8
2-8, 39
O
ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4).
These lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held
at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold
acknowledge” or “grant sequence”.
A19/S6,
A18/S5,
A17/S4,
A16/S3
35
36
37
38
O
O
O
O
ADDRESS/STATUS: During T1, these are the four most
significant address lines for memory operations. During
I/O operations, these lines are LOW. During memory and
I/O operations, status information is available on these
lines during T2, T3, TW and T4. S6 is always LOW. The
status of the interrupt enable flag bit (S5) is updated at the
beginning of each clock cycle. S4 and S3 are encoded as
shown.
This information indicates which segment register is
presently being used for data accessing.
These lines are held at high impedance to the last valid
logic level during local bus “hold acknowledge” or “grant
Sequence”.
RD
32
O
READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depend-
ing on the state of the IO/M pin or S2. This signal is used to read devices which reside on the 80C88
local bus. RD is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH
in T2 until the 80C88 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.
READY
22
I
READY: is the acknowledgment from the address memory or I/O device that it will complete the data
transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from
READY. This signal is active HIGH. The 80C88 READY input is not synchronized. Correct operation
is not guaranteed if the set up and hold times are not met.
INTR
18
I
INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of
each instruction to determine if the processor should enter into an interrupt acknowledge operation.
A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be
internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This
signal is active HIGH.
TEST
23
I
TEST: input is examined by the “wait for test” instruction. If the TEST input is LOW, execution con-
tinues, otherwise the processor waits in an “idle” state. This input is synchronized internally during
each clock cycle on the leading edge of CLK.
NMI
17
I
NONMASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A sub-
routine is vectored to via an interrupt vector lookup table located in system memory. NMI is not
maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end
of the current instruction. This input is internally synchronized.
RESET
21
I
RESET: cases the processor to immediately terminate its present activity. The signal must transition
LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as de-
scribed in the instruction set description, when RESET returns LOW. RESET is internally synchro-
nized.
CLK
19
I
CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33%
duty cycle to provide optimized internal timing.
V
CC
40
V
CC
: is the +5V power supply pin. A 0.1
μ
F capacitor between pins 20 and 40 recommended for de-
coupling.
GND
1, 20
GND: are the ground pins (both pins must be connected to system ground). A 0.1
μ
F capacitor be-
tween pins 1 and 20 is recommended for decoupling.
MN/MX
33‘
I
MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are
discussed in the following sections.
S4
S3
CHARACTERISTICS
0
0
Alternate Data
0
1
Stack
1
0
Code or None
1
1
Data
80C88
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