參數(shù)資料
型號： LSIFC929
英文描述： LSIFC929 dual channel fibre solutions
中文描述： LSIFC929雙通道光纖解決方案
文件頁數(shù)： 48/144頁
文件大?。?/td> 1496K
代理商： LSIFC929
4-8
Signal Descriptions
Table 4.3
describes the FC G-bit Interface signals.
Table 4.3
FC G-Bit Interface Signals
Name
BGA Pos
Type Strength Description
TX+
M2
O
N/A
Transmit differential data.
TX
L2
O
N/A
Transmit differential data.
RX+
J2
I
N/A
Receive differential data.
RX
H2
I
N/A
Receive differential data.
IREF
K1
I
N/A
Analog current reference
for the integrated transceiver
core. A 2.74 k
resistor should be tied from the IREF pad
to ground.
LIPRESET/ J3
O
4 mA
LIP Reset.
This pin is asserted LOW when a selective
reset is received that is targeted to one of this device’s
aliases. This pin is asserted for 1–2 ms after the last LIP
Reset is received.
FAULT/
U3
I
N/A
Fault.
This pin indicates that an electrical fault has been
detected by the PHY device/module and, if the module
has a laser, the laser has been turned off. This pad
contains an internal 100
μ
A pull-up.
ODIS
C4
O
4 mA
Output Disable.
This output, when asserted, disables an
external GBIC or Media Interface Adapter (MIA)
transmitter. This output is also used to clear a module
fault.
BYPASS/
H4
O
4 mA
Bypass.
This line is driven LOW when the LSIFC909 Link
Controller block has determined that the device is
operating in a loop environment and the device has
entered a bypass mode. This may be caused by an
internal request or a loop primitive generated by another
node.
WMSEL
C8
I
N/A
WaveMaker (Integrated Transceiver) Select.
When
asserted HIGH, the integrated transceiver is enabled.
When deasserted, the 10-bit interface is enabled, and an
external PHY device is required. This pad contains an
internal 100
μ
A pull-up.
REFCLK
N1
I
N/A
FC reference clock
. (106.25 MHz
±
100 ppm).
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