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| 型號： | LT1007IS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PREC OP-AMP HI-SPD SNGL 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 2.5 V/µs |
| 增益帶寬積： | 8MHz |
| 電流 - 輸入偏壓： | 15nA |
| 電壓 - 輸入偏移： | 20µV |
| 電壓 - 電源，單路/雙路(±)： | ±4 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1317 (CN2011-ZH PDF) |
4
LT1007/LT1037
sn100737 100737fbs
The q denotes the specifications which apply over the temperature range – 40
°C ≤ TA ≤ 85°C, VS = ±15V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
For MIL-STD components, please refer to LTC 883C data sheet for test
listing and parameters.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Input Offset Voltage measurements are performed by automatic
test equipment approximately 0.5 seconds after application of power. AM
and AC grades are guaranteed fully warmed up.
Note 3: Long Term Input Offset Voltage Stability refers to the average
trend line of Offset Voltage vs Time over extended periods after the first 30
days of operation. Excluding the initial hour of operation, changes in VOS
during the first 30 days are typically 2.5
V. Refer to typical performance
curve.
Note 4: This parameter is tested on a sample basis only.
Note 5: 10Hz noise voltage density is sample tested on every lot. Devices
100% tested at 10Hz are available on request.
Note 6: See the test circuit and frequency response curve for 0.1Hz to
10Hz tester in the Applications Information section.
Note 7: See the test circuit for current noise measurement in the
Applications Information section.
Note 8: This parameter is guaranteed by design and is not tested.
Note 9: The inputs are protected by back-to-back diodes. Current limiting
resistors are not used in order to achieve low noise. If differential input
voltage exceeds
±0.7V, the input current should be limited to 25mA.
Note 10: The Average Input Offset Drift performance is within the
specifications unnulled or when nulled with a pot having a range of 8k
to
20k
.
The q denotes the specifications which apply over the temperature range – 55
°C ≤ TA ≤ 125°C, VS = ±15V, unless otherwise noted.
LT1007I/LT1037I
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOS
Input Offset Voltage
(Note 2)
q
40
125
V
VOS
Average Input Offset Drift
(Note 10)
q
0.3
1.0
V/°C
Temp
IOS
Input Offset Current
q
20
80
nA
IB
Input Bias Current
q
±25
±90
nA
Input Voltage Range
q
±10
±11.7
V
CMRR
Common Mode Rejection Ratio
VCM = ±10.5V
q
105
120
dB
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ±18V
q
101
120
dB
AVOL
Large-Signal Voltage Gain
RL ≥ 2k, VO = ±10V
q
2.0
15.0
V/
V
RL ≥ 1k, VO = ±10V
q
1.5
12.0
V/
V
VOUT
Maximum Output Voltage Swing
RL ≥ 2k
q
±12.0 ±13.6
V
PD
Power Dissipation
q
95
165
mW
LT1007AM/LT1037AM
LT1007M/LT1037M
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
VOS
Input Offset Voltage
(Note 2)
q
25
60
50
160
V
VOS
Average Input Offset Drift
(Note 10)
q
0.2
0.6
0.3
1.0
V/°C
Temp
IOS
Input Offset Current
q
15
50
20
85
nA
IB
Input Bias Current
q
±20
±60
±35
±95
nA
Input Voltage Range
q
±10.3 ±11.5
V
CMRR
Common Mode Rejection Ratio
VCM = ±10.3V
q
112
126
104
120
dB
PSRR
Power Supply Rejection Ratio
VS = ±4.5V to ±18V
q
104
126
100
120
dB
AVOL
Large-Signal Voltage Gain
RL ≥ 2k, VO = ±10V
q
3.0
14.0
2.0
14.0
V/
V
RL ≥ 1k, VO = ±10V
q
2.0
10.0
1.5
10.0
V/
V
VOUT
Maximum Output Voltage Swing
RL ≥ 2k
q
±12.5 ±13.5
±12.0 ±13.5
V
PD
Power Dissipation
q
100
150
100
170
mW
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