8
LT1191
FREQUENCY (Hz)
CLOSED-LOOP
VOLTAGE
GAIN
(dB)
20
10
0
–10
–20
1G
LT1191 TA05
100M
10M
1M
100k
VS = ±5V
TA = 25°C
RL = 1k
A = 2
V
A = 1
V
Power Supply Bypassing
The LT1191 is quite tolerant of power supply bypassing. In
some applications a 0.1
F ceramic disc capacitor placed
1/2 inch from the amplifier is all that is required. A scope
photo of the amplifier output with no supply bypassing is
used to demonstrate this bypassing tolerance, RL = 1k.
Supply bypassing can also affect the response in the
frequency domain. It is possible to see a slight rise in the
frequency response at 130MHz depending on the gain
configuration, supply bypass, inductance in the supply
leads and printed circuit board layout. This can be further
minimized by not using a socket.
In most applications, and those requiring good settling
time, it is important to use multiple bypass capacitors. A
0.1
F ceramic disc in parallel with a 4.7F tantalum is
recommended. Two oscilloscope photos with different
bypass conditions are used to illustrate the settling time
characteristics of the amplifier. Note that although the
output waveform looks acceptable at 1V/DIV, when ampli-
fied to1mV/DIV the settling time to 2mV is 2.61
s for the
0.1
F bypass; the time drops to 143ns with multiple
bypass capacitors.
Settling Time Poor Bypass
Settling Time Good Bypass
Closed-Loop Voltage Gain vs Frequency
No Supply Bypass Capacitors
LT1191 TA04
AV = –1, IN DEMO BOARD, RL = 1k
LT1191 TA06
SETTLING TIME TO 2mV, AV = –1
SUPPLY BYPASS CAPACITORS = 0.1
F
LT1191 TA07
SETTLING TIME TO 2mV, AV = –1
SUPPLY BYPASS CAPACITORS = 0.1
F + 4.7F TANTALUM
VOUT
1V/DIV
VOUT
1mV/DIV
0V
VOUT
1mV/DIV
0V
APPLICATIO S I FOR ATIO
WU
UU
0V
VOUT
1V/DIV
0V