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| 型號： | LT1469CDF-2#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP 16BIT DUAL 200MHZ 12DFN |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 30 V/µs |
| 增益帶寬積： | 200MHz |
| 電流 - 輸入偏壓： | 10nA |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 4.1mA |
| 電流 - 輸出 / 通道： | 22mA |
| 電壓 - 電源，單路/雙路(±)： | ±2.5 V ~ 18 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 12-DFN-EP（4x4） |
| 包裝： | 管件 |
LT1469-2
9
14692f
APPLICATIONS INFORMATION
Gain of 2 Stable
The LT1469-2 is a decompensated version of the LT1469.
The DC precision performance is identical, but the internal
compensation capacitors have been reduced to a point
where the op amp needs a gain of 2 or greater in order
to be stable.
In general, for applications where the gain around the op
amp is ≥ 2, the decompensated version should be used,
because it will give the best AC performance. In applica-
tions where the gain is <2, the unity-gain stable version
should be used.
The appropriate way to dene the ‘gain’ is as the inverse
of the feedback ratio from output to differential input,
including all relevant parasitics. Moreover, as with all
feedback loops, the stability of the loop depends on the
value of that feedback ratio at frequencies where the total
loop-gain would cross unity. Therefore, it is possible to
have circuits in which the gain at DC is lower than the gain
at high frequency, and these circuits can be stable even
with a non unity-gain stable op amp. An example is many
current-output DAC buffer applications.
Layout and Passive Components
The LT1469 requires attention to detail in board layout
in order to maximize DC and AC performance. For best
AC results (for example, fast settling time) use a ground
plane, short lead lengths and RF quality bypass capacitors
(0.01μF to 0.1μF) in parallel with low ESR bypass capaci-
tors (1μF to 10μF tantalum). For best DC performance, use
“star” grounding techniques, equalize input trace lengths
and minimize leakage (e.g., 1.5GΩ of leakage between an
input and a 15V supply will generate 10nA—equal to the
maximum IB– specication).
Board leakage can be minimized by encircling the input
circuitry with a guard ring operated at a potential close
to that of the inputs: for inverting congurations tie the
ring to ground, in noninverting connections tie the ring
to the inverting input (note the input capacitance will
increase which may require a compensating capacitor as
discussed below).
Microvolt level error voltages can also be generated in
the external circuitry. Thermocouple effects caused by
temperature gradients across dissimilar metals at the
contacts to the inputs can exceed the inherent drift of
the amplier. Air currents over device leads should be
minimized, package leads should be short and the two
input leads should be as close together as possible and
maintained at the same temperature.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with the
input capacitance to form a pole which can cause peak-
ing or even oscillations. A feedback capacitor of value CF
= RG CIN/RF may be used to cancel the input pole and
optimize dynamic performance. For applications where
the DC noise gain is one, and a large feedback resistor is
used, CF should be less than or equal to one half of CIN.
An example would be a DAC I-to-V converter as shown on
the front page of the data sheet where the DAC can have
many tens of picofarads of output capacitance.
Figure 1. Nulling Input Capacitance
Figure 2. Input Stage Protection
+
–
VOUT
RF
CF
CIN 1/2 LT1469-2
VIN
14692 F01
RG
Q1
+IN
14692 F02
R1
100Ω
Q2
–IN
R1
100Ω
V–
V+
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