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參數(shù)資料
| 型號(hào)： | LT1533CS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS |
| 中文描述： | 1.8 A SWITCHING REGULATOR, 250 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件頁(yè)數(shù)： | 10/20頁(yè) |
| 文件大?。?/td> | 379K |
| 代理商： | LT1533CS |
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10
LT1533
APPLICATIO
S I
N
FOR
ATIO
U
Thermal Considerations
Computing power dissipation for this IC requires careful
attention to detail. Reduced output slewing causes the part
to dissipate more power than would occur with fast edges.
However, much improvement in noise can be produced
with modest decrease in supply efficiency.
Power dissipation is a function of topology, input voltage,
switch current and slew rates. It is impractical to come up
with an all-encompassing formula. It is therefore recom-
mended that package temperature be measured in each
application. The part has an internal thermal shutdown to
prevent device destruction, but this should not replace
careful thermal design.
1. Dissipation due to input current:
W
U
where
I is the ripple current in the switch, R
CSL
and
R
VSL
are the slew resistors and f
OSC
is the oscillator
frequency.
Power dissipation P
D
is the sum of these three terms. Die
junction temperature is then computed as:
T
J
= T
AMB
+ (P
D
)(
θ
JA
)
where T
AMB
is ambient temperature and
θ
JA
is the package
thermal resistance. For the 16-pin SO
θ
JA
is 100
°
C/W.
For example, with f
OSC
= 40kHz, V
IN
= 10V, 0.4A average
current and 0.1A of ripple, the maximum duty cycle is
44%. Assume slew resistors are both 17k and V
SAT
is
0.26V, then:
P
D
= 0.176W + 0.094W + 0.158W = 0.429W
In an S16 package the die junction temperature would be
43
°
C above ambient.
Frequency Compensation
Loop frequency compensation is accomplished by way of
a series RC network on the output of the error amplifier (V
C
pin). Referring to Figure 3, the main pole is formed by
capacitor C
VC
and the output impedance of the error
amplifier (approximately 400k
). The series resistor R
VC
creates a “zero” which improves loop stability and tran-
sient response. A second capacitor C
VC2
, typically one-
tenth the size of the main compensation capacitor, is
sometimes used to reduce the switching frequency ripple
on the V
C
pin. V
C
pin ripple is caused by output voltage
ripple attenuated by the output divider and multiplied by
the error amplifier. Without the second capacitor, V
C
pin
ripple is:
=
(
V
V
g
R
V
C PIN RIPPLE
RIPPLE
m
VC
OUT
)(
)( )(
)
1 25
where V
RIPPLE
= Output ripple (V
P-P
)
g
m
= Error amplifier transconductance
R
VC
= Series resistor on V
C
pin
V
OUT
= DC output voltage
P
V
mA
I
VIN
IN
=
+
11
60
where I is the average switch current.
2. Dissipation due to the drivers saturation:
P
VSAT
= (V
SAT
)(I)(DC
MAX
)
where V
SAT
is the output saturation voltage which is
approximately 0.1 + (0.4)(I), DC
MAX
is the maximum
duty cycle.
3. Dissipation due to output slew using approximations
for slew rates:
P
V
I
I
R
I V
()
V
R
f
SLEW
IN
CSL
IN
SAT
4
VSL
OSC
=
( )
( )
+
(
)
+
(
(
)
(
)
2
2
9
2
2
9
4
220 10
Note if V
SAT
and
I are small with respect to V
IN
and I,
then:
P
()(
( )
V
R
f
V
I
SLEW
CSL
VSL
OSC
IN
=
)
+
( )(
(
)
(
)( )()
220 10
9
9
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