參數(shù)資料
型號(hào)： LT1739IFE#TR
廠商： Linear Technology
文件頁(yè)數(shù)： 20/20頁(yè)
文件大小： 0K
描述： IC AMP XDSL LINE DRV DUAL20TSSOP
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 線路驅(qū)動(dòng)器，發(fā)射器
驅(qū)動(dòng)器/接收器數(shù)： 2/0
電源電壓： 5 V ~ 12 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 20-TSSOP-EP
包裝： 帶卷 (TR)
其它名稱： LT1739IFETR
9
LT1739
1739fas, sn1739
the design of the PCB and card enclosure to take measures
to spread the heat developed in the driver away to the
ambient environment to prevent thermal shutdown (which
occurs when the junction temperature of the LT1739
exceeds 165
°C).
Estimating Line Driver Power Dissipation
Figure 6 is a typical ADSL application shown for the
purpose of estimating the power dissipation in the line
driver. Due to the complex nature of the DMT signal,
which looks very much like noise, it is easiest to use the
RMS values of voltages and currents for estimating the
driver power dissipation. The voltage and current levels
shown for this example are for a full-rate ADSL signal
driving 20dBm or 100mWRMS of power on to the 100
telephone line and assuming a 0.5dBm insertion loss in
the transformer. The quiescent current for the LT1739 is
set to 10mA per amplifier.
The power dissipated in the LT1739 is a combination of the
quiescent power and the output stage power when driving
a signal. The two amplifiers are configured to place a
differential signal on to the line. The Class AB output stage
in each amplifier will simultaneously dissipate power in
the upper power transistor of one amplifier, while sourc-
ing current, and the lower power transistor of the other
amplifier, while sinking current. The total device power
dissipation is then:
PD = PQUIESCENT + PQ(UPPER) + PQ(LOWER)
PD = (V+ – V–) IQ + (V+ – VOUTARMS)
ILOAD + (V – – VOUTBRMS) ILOAD
With no signal being placed on the line and the amplifier
biased for 10mA per amplifier supply current, the quies-
cent driver power dissipation is:
PDQ = 24V 20mA = 480mW
This can be reduced in many applications by operating
with a lower quiescent current value.
When driving a load, a large percentage of the amplifier
quiescent current is diverted to the output stage and
becomes part of the load current. Figure 7 illustrates the
total amount of biasing current flowing between the + and
– power supplies through the amplifiers as a function of
load current. As much as 60% of the quiescent no load
operating current is diverted to the load.
APPLICATIO S I FOR ATIO
WU
UU
Figure 6. Estimating Line Driver Power Dissipation
1739 F06
+
–
B
–IN
–
+
A
+IN
12V
20mA DC
SHDN
–12V
–2VRMS
17.4
24.9k – SETS IQ PER AMPLIFIER = 10mA
1:1.7
110
1000pF
110
1k
17.4
SHDNREF
100
3.16VRMS
ILOAD = 57mARMS
2VRMS
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