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參數(shù)資料
| 型號： | LT1970IFE |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OP AMP 500MA ADJ 20-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 1.6 V/µs |
| 增益帶寬積： | 3.6MHz |
| 電流 - 輸入偏壓： | 160nA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 7mA |
| 電流 - 輸出 / 通道： | 800mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 36 V，±2.5 V ~ 18 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP-EP |
| 包裝： | 管件 |
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LT1970
17
1970fc
APPLICATIONS INFORMATION
VDIODE is less than the voltage across RSENSE. Adding an
optional external 100Ω resistor in parallel with the internal
1k resistor forces the diode voltage closer to the sensed
current limit voltage and reduces the current limit error.
Alternatively, the base-emitter junctions of back-to-back
2N3904 NPN transistors can provide this clamping action.
These diodes begin to conduct at a higher voltage level
nearer to 600mV. With a 500mV maximum current limit
threshold very little error will be noticed. Comparisons
of typical current limit error with three ways of adding
clamping protection are shown in Figure 8. Scaling the
current sense resistor and the current limit control voltage
down so that a 0V to 300mV current limit sense voltage
range also prevents these accuracy errors caused by the
abrupt-short clamping diodes.
Also shown in Figure 7 is a small ltering capacitor. This
too provides an extra measure of control under abrupt
load shorting conditions. A fast short-circuit makes ap-
parent all parasitic interconnect lead inductances between
the LT1970 and the load. These distributed parasitic ele-
ments can cause signicant transient voltage spikes in
the short time after the application or removal of a short
circuit. These uncontrolled voltage transients could actu-
ally couple back to the current limit amplier and cause
polarity reversal from sourcing current limit to sinking or
vice versa. This can act as positive feedback and cause
the current limit amplier to go to the incorrect current
limit direction and hang up. Adding a small lter capaci-
tor between the SENSE– and FILTER pins, 1nF to 10nF is
fairly typical, which charges through the clamp diodes
forces the correct current limit polarity at the instant of the
load short. This holds the amplier in current limit until
the capacitor discharges through the internal 1k resistor,
eliminating transient induced behavior and creating a
smooth transition into current limit.
Supply Bypassing
The LT1970 can supply large currents from the power
supplies to a load at frequencies up to 4MHz. Power sup-
ply impedance must be kept low enough to deliver these
currents without causing supply rails to droop. Low ESR
capacitors, such as 0.1μF or 1μF ceramics, located close to
the pins are essential in all applications. When large, high
speed transient currents are present additional capacitance
may be needed near the chip. Check supply rails with a
scope and if signal related ripple is seen on the supply rail,
increase the decoupling capacitor as needed.
To ensure proper start-up biasing of the LT1970, it is rec-
ommended that the rate of change of the supply voltages
at turn-on be limited to be no faster than 6V/μs.
Application Circuit Ideas
The digitally controlled analog pin driver is shown in
Figure 9. All of the control signals are provided by an
LTC1664 quad, 10-bit DAC by way of a 3-wire serial
interface. The LT1970 is congured as a simple differ-
ence amplier with a gain of 3. This gain is required to
produce ±15V from the 0V to 5V outputs from DACs C
and D. To provide voltage headroom, the supplies for the
LT1970 are set to the maximum value of ±18V. As ±18V
is the absolute maximum rating of supply voltage for the
LT1970, care must be taken to not allow the supply voltage
to increase. DACs A and B separately control the sinking
and sourcing current limit to the load over the range of
± 4mA to ±500mA. An optional ON/OFF control for the pin
driver using the ENABLE input is shown. If always enabled
the ENABLE pin should be tied to VCC.
Figure 8. Current Limit Accuracy with Different Clamps
±VCL SENSE (mV)
50
–10
CURRENT
LIMIT
ACCURACY
(%)
–5
5
10
15
25
100
300
400
1970 F08
0
20
250
500
150 200
350
450
2N3904 w 1kΩ
BAV99 w 1kΩ
BAV99 w 100Ω
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LT1970IFE#PBF | 功能描述:IC OP AMP 500MA ADJ 20-TSSOP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:- 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
| LT1970IFE#PBF | 制造商:Linear Technology 功能描述:OP-AMP PRECISION 3.6MHZ 1.6 制造商:Linear Technology 功能描述:OP-AMP, PRECISION, 3.6MHZ, 1.6V/uS, TSSO |
| LT1970IFE#TR | 功能描述:IC OPAMP ADJ PREC 500MA 20TSSOP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 |
| LT1970IFE#TRPBF | 功能描述:IC OP AMP 500MA ADJ 20-TSSOP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:3.5 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:30pA 電壓 - 輸入偏移:2000µV 電流 - 電源:200µA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 |
| LT1970IFEPBF | 制造商:Linear Technology 功能描述:Op Amp Gen.Purpose +/-18V/36V TSSOP20EP |
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