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參數(shù)資料
| 型號： | LTAEY |
| 廠商： | Linear Integrated Systems |
| 英文描述： | Differential Input 16-Bit No Latency DS ADC |
| 中文描述： | 差分輸入16位ADC的無延遲局副局長 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 298K |
| 代理商： | LTAEY |
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LTC2433-1
16
24331fa
and the device begins outputting data at time t
EOCtest
after
the falling edge of CS (if EOC = 0) or t
EOCtest
after EOC goes
LOW (if CS is LOW during the falling edge of EOC). The
value of t
EOCtest
is 23
μ
s if the device is using its internal
oscillator (F
0
= logic LOW). If F
O
is driven by an external
oscillator of frequency f
EOSC
, then t
EOCtest
is 3.6/f
EOSC
. If
CS is pulled HIGH before time t
EOCtest
, the device returns
to the sleep state and the conversion result is held in the
internal static shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle concludes
after the 19th rising edge. Data is shifted out the SDO pin
on each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used to
shift the conversion result into external circuitry. EOC can
be latched on the first rising edge of SCK and the last bit
of the conversion result on the 19th rising edge of SCK.
After the 19th rising edge, SDO goes HIGH (EOC = 1), SCK
stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 19th rising edge of
SCK, see Figure 10. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for aborting an invalid
conversion cycle, or synchronizing the start of a conver-
sion. If CS is pulled HIGH while the converter is driving
SCK LOW, the internal pull-up is not available to restore
SCK to a logic HIGH state. This will cause the device to exit
the internal serial clock mode on the next falling edge of
CS. This can be avoided by adding an external 10k pull-up
resistor to the SCK pin or by never pulling CS HIGH when
SCK is LOW.
Whenever SCK is LOW, the LTC2433-1’s internal pull-up
at pin SCK is disabled. Normally, SCK is not externally
driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a
LOW signal, the LTC2433-1’s internal pull-up remains
Figure 9. Internal Serial Clock, Single Cycle Operation
SDO
SCK
(INTERNAL)
CS
MSB
SIG
“O”
BIT 0
LSB
BIT 2
BIT 1
TEST EOC
BIT 14
BIT 13
BIT 15
BIT 16
BIT 17
EOC
BIT 18
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
24331 F09
<t
EOCtest
V
CC
10k
Hi-Z
Hi-Z
Hi-Z
Hi-Z
TEST EOC
(OPTIONAL)
SLEEP
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
GND
SDO
CS
1
10
2
3
9
4
5
6
8
7
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1
μ
F
2.7V TO 5.5V
LTC2433-1
3-WIRE
SPI INTERFACE
APPLICATIOU
W
U
U
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