7
LTC1062
1062fd
Divide By 1, 2, 4 (Pin 4)
By connecting Pin 4 to V+, to mid supplies or to V–, the
clock frequency driving the internal switched capacitor
network is the oscillator frequency divided by 1, 2, 4
respectively. Note that the fCLK/fC ratio of 100:1 is with
respect to the internal clock generator output frequency.
The internal divider is useful for applications where octave
tuning is required. The ÷2 threshold is typically ±1V from
the mid supply voltage.
Transient Response
Figure 3 shows the LTC1062 response to a 1V input step.
Filter Noise
The filter wideband RMS noise is typically 100VRMS for
±5V supply and it is nearly independent from the value of
the cutoff frequency. For single 5V supply the RMS noise
is 80VRMS. Sixty-two percent of the wideband noise is in
the passband, that is from DC to fC. The noise spectral
density, unlike conventional active filters, is nearly zero for
frequencies below 0.1 fC. This is shown in the Typical
Performance Characteristics section. Table 2 shows the
LTC1062 RMS noise for different noise bandwidths.
Table 2
NOISE BW
RMS NOISE (VS = ±5V)
DC – 0.1 fC
2V
DC – 0.25 fC
8V
DC – 0.5 fC
20V
DC – 1 fC
62V
DC – 2 fC
100V
200mV/VERT DIV
50ms/HORIZ DIV, fC = 10Hz
5ms/HORIZ DIV, fC = 100Hz
0.5ms/HORIZ DIV, fC = 1kHz
1
2πRC
fC
1.62
=
1
2πRC
fC
1.94
=
1
2πRC
fC
2.11
=
Figure 3. Step Response to a 1V Peak Input Step
APPLICATIO S I FOR ATIO
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