The first “l(fā)ogical one” clocked into the D
參數(shù)資料
型號: LTC1094ACN
廠商: Linear Technology
文件頁數(shù): 6/32頁
文件大小: 0K
描述: IC DATA ACQ SYS 10BIT 8CH 20-DIP
標準包裝: 18
類型: 數(shù)據(jù)采集系統(tǒng)(DAS),ADC
分辨率(位): 10 b
數(shù)據(jù)接口: 串行
電壓電源: 雙 ±
電源電壓: ±5V,4.5V,10V
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 20-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 20-PDIP
包裝: 管件
14
LTC1091/LTC1092
LTC1093/LTC1094
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
Start Bit
The first “l(fā)ogical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
transfer. The LTC1091/LTC1093/LTC1094 will ignore all
leading zeros which precede this logical one. After the start
bit is received, the remaining bits of the input word will be
clocked in. Further inputs on the DIN pin are then ignored
until the next CS cycle.
Multiplexer (MUX) Address
The bits of the input word following the START bit assign
the MUX configuration for the requested conversion. For
a given channel selection, the converter will measure the
voltage between the two channels indicated by the + and
– signs in the selected row of the following tables. In
single-ended mode, all input channels are measured with
respect to GND on the LTC1091 and COM on the
LTC1093/LTC1094.
SINGLE-ENDED
MUX MODE
MUX ADDRESS
CHANNEL #
GND
DIFFERENTIAL
MUX MODE
SGL/
DIFF
1
0
ODD/
SIGN
0
1
0
1
0
+
1
+
+
1091-4 AI08
LTC1091 Channel Selection
MUX ADDRESS
SELECT
DIFFERENTIAL CHANNEL SELECTION
SGL/
DIFF
0
ODD/
SIGN
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
+
1
+
2
+
3
+
4
+
5
+
1091-4 AI09
NOT USED
MUX ADDRESS
SELECT
SINGLE-ENDED CHANNEL SELECTION
SGL/
DIFF
1
ODD/
SIGN
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
+
1
+
2
+
3
+
4
+
5
+
COM
NOT USED
LTC1093 Channel Selection
MUX ADDRESS
SELECT
DIFFERENTIAL CHANNEL SELECTION
SGL/
DIFF
0
ODD/
SIGN
0
1
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
+
1
+
2
+
3
+
4
+
5
+
6
+
7
+
1091-4 AI0
MUX ADDRESS
SELECT
SINGLE-ENDED CHANNEL SELECTION
SGL/
DIFF
1
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
+
1
+
2
+
3
+
4
+
5
+
6
+
7
+
COM
ODD/
SIGN
0
1
LTC1094 Channel Selection
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