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參數(shù)資料
| 型號： | LTC1283AC |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 3V Single Chip 10-Bit Data Acquisition System |
| 中文描述： | 3V的單芯片10位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 452K |
| 代理商： | LTC1283AC |
20
LTC1283
U
S
A
O
PPLICATI
U
U
differencing operation may not be performed accurately.
The conversion time is 44 ACLK cycles. Therefore, a
change in the “–” input voltage during this interval can
cause conversion errors. For a sinusoidal voltage on the
“–” input this error would be:
V
ERROR (MAX)
= V
PEAK
×
2
×
π
×
f(“–”)
×
44/f
ACLK
Where f(“–”) is the frequency of the “–” input voltage,
V
PEAK
is its peak amplitude and f
ACLK
is the frequency of
the ACLK. In most cases V
ERROR
will not be significant. For
a 60Hz signal on the “–” input to generate a 1/4LSB error
(0.61mV) with the converter running at ACLK = 1MHz, its
peak value would have to be 38mV.
5. Reference Inputs
The voltage between the reference inputs of the LTC1283
defines the voltage span of the A/D converter. The refer-
ence inputs look primarily like a 10k resistor but will have
transient capacitive switching currents due to the switched-
capacitor conversion technique (see Figure 14). During
each bit test of the conversion (every 4 ACLK cycles), a
capacitive current spike will be generated on the reference
pins by the A/D. These current spikes settle quickly and do
not cause a problem. However, if slow settling circuitry is
used to drive the reference inputs, care must be taken to
insure that transients caused by these current spikes settle
completely during each bit test of the conversion.
show examples of both adequate and poor settling.
Using a slower ACLK will allow more time for the refer-
ence to settle. However, even at the maximum ACLK rate
of 1MHz most references and op amps can be made to
settle within the 4
μ
s bit time.
3. It is recommended that the REF
–
input be tied directly to
the analog ground plane. If REF
–
is biased at a voltage
other than ground, the voltage must not change during a
conversion cycle. This voltage must also be free of noise
and ripple with respect to analog ground.
R
ON
5pF TO 30pF
LTC1283
REF
+
14
R
OUT
V
REF
EVERY 4 ACLK CYCLES
13
REF
–
LTC1283 F14
10k
TYP
When driving the reference inputs, three things should be
kept in mind:
1. The source resistance (R
OUT
) driving the reference
inputs should be low (less than 1
) to prevent DC drops
caused by the 300
μ
A maximum reference current (I
REF
).
2. Transients on the reference inputs caused by the capaci-
tive switching currents must settle completely during
each bit test (each 4 ACLK cycles). Figures 15 and 16
Figure 14. Reference Input Equivalent Circuit
Figure 15. Adequate Reference Settling
6. Reduced Reference Operation
The effective resolution to the LTC1283 can be increased by
reducing the input span of the converter. The LTC1283
exhibits good linearity and gain over a wide range of
reference voltages (see typical curves of Linearity and Gain
Error vs Reference Voltage). However, care must be
taken
Figure 16. Poor Reference Settling Can Cause A/D Errors
HORIZONTAL: 1
μ
s/DIV
V
V
HORIZONTAL: 1
μ
s/DIV
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| LTC1283ACN | 3V Single Chip 10-Bit Data Acquisition System |
| LTC1283ACS | 3V Single Chip 10-Bit Data Acquisition System |
| LTC1283C | 3V Single Chip 10-Bit Data Acquisition System |
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