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參數(shù)資料
| 型號(hào)： | LTC1283AC |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 3V Single Chip 10-Bit Data Acquisition System |
| 中文描述： | 3V的單芯片10位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 6/24頁 |
| 文件大小： | 452K |
| 代理商： | LTC1283AC |
6
LTC1283
C
HARA TERISTICS
U
A
TYPICAL PERFOR
CE
Sample-and-Hold Acquisition
Time vs Source Resistance
Input Channel Leakage Current
vs Temperature
Noise Error
vs Reference Voltage
REFERENCE VOLTAGE (V)
0
0
P
0.2
0.4
0.6
0.8
1.0
1.2
0.5
1.0
1.5
2.0
LTC1283 G15
2.5
V
CC
= 3V
ACLK = 500kHz
LTC1283 NOISE = 200
μ
V
P-P
AMBIENT TEMPERATURE (°C)
–50
0.01
I
0.1
1
10
100
–25
0
25
50
LTC1283 G14
75
100
125
V
CC
= 3V
V
REF
= 2.5V
ON
CHANNEL
OFF
CHANNEL
1000
GUARANTEED
PI FU
U
#
PIN
FUNCTION
DESCRIPTION
1-8
9
CH0-CH7
COM
Analog Inputs
Common
The analog inputs must be free of noise with respect to AGND.
The common pin defines the zero reference point for all single-ended inputs. It must be
free of noise and is usually tied to the analog ground plane.
This is the ground for the internal logic. Tie to the ground plane.
AGND should be tied directly to the analog ground plane.
Tie V
–
to most negative potential in the circuit. (Ground in single supply applications.)
The reference inputs must be kept free of noise with respect to AGND.
A logic low on this input enables data transfer.
The A/D conversion result is shifted out of this output.
The A/D configuration word is shifted into this input.
This clock synchronizes the serial data transfer.
This clock controls the A/D conversion process.
This supply must be kept free of noise and ripple by bypassing directly to the analog
ground plane.
10
11
12
13, 14
15
16
17
18
19
20
DGND
AGND
V
–
REF
–
, REF
+
CS
D
OUT
D
IN
SCLK
ACLK
V
CC
Digital Ground
Analog Ground
Negative Supply
Reference Inputs
Chip Select Input
Digital Data Output
Data Input
Shift Clock
A/D Conversion Clock
Positive Supply
W
IAGRA
BLOCK
R
SOURCE
(k
)
0.1
1
S
μ
s
10
9
8
7
6
1
10
LTC1283 G13
5
V
CC
= 3V
V
REF
= 2.5V
T
= 25°C
0V TO 2.5V INPUT STEP
+
–
V
IN
R
SOURCE
+
4
3
2
INPUT
SHIFT
REGISTER
SAMPLE-
AND-
HOLD
10-BIT
CAPACITIVE
DAC
V
CC
20
ANALOG
INPUT MUX
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
D
OUT
16
SCLK
18
CONTROL
AND
TIMING
15
CS
LTC1283 BD
17
REF
+
14
DGND
10
AGND
11
V
–
12
REF
–
13
COMP
OUTPUT
SHIFT
REGISTER
D
IN
19
ACLK
10-BIT
SAR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC1283ACN | 3V Single Chip 10-Bit Data Acquisition System |
| LTC1283ACS | 3V Single Chip 10-Bit Data Acquisition System |
| LTC1283C | 3V Single Chip 10-Bit Data Acquisition System |
| LTC1283CN | 3V Single Chip 10-Bit Data Acquisition System |
| LTC1283CS | 3V Single Chip 10-Bit Data Acquisition System |
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