參數(shù)資料
型號(hào): LTC1283ACN#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 21/24頁(yè)
文件大小: 0K
描述: IC DATA ACQ SYS 10BIT 3V 20-DIP
標(biāo)準(zhǔn)包裝: 18
類型: 數(shù)據(jù)采集系統(tǒng)(DAS)
分辨率(位): 10 b
采樣率(每秒): 15k
數(shù)據(jù)接口: 串行,并聯(lián)
電壓電源: 雙 ±
電源電壓: ±3.3V,3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 20-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 20-PDIP
包裝: 管件
6
LTC1283
1283fb
CC
HARA TERISTICS
UW
A
TYPICALPERFOR
CE
Sample-and-Hold Acquisition
Time vs Source Resistance
Input Channel Leakage Current
vs Temperature
Noise Error
vs Reference Voltage
REFERENCE VOLTAGE (V)
0
PEAK-TO-PEAK
NOISE
ERROR
(LSB
)
0.2
0.4
0.6
0.8
1.0
1.2
0.5
1.0
1.5
2.0
LTC1283 G15
2.5
VCC = 3V
ACLK = 500kHz
LTC1283 NOISE = 200
μVP-P
AMBIENT TEMPERATURE (°C)
–50
0.01
INPUT
CHANNEL
LEAKAGE
CURRENT
(nA)
0.1
1
10
100
–25
0
25
50
LTC1283 G14
75
100
125
VCC = 3V
VREF = 2.5V
ON
CHANNEL
OFF
CHANNEL
1000
GUARANTEED
PI FU CTIO S
U
UU
#
PIN
FUNCTION
DESCRIPTION
1-8
CH0-CH7
Analog Inputs
The analog inputs must be free of noise with respect to AGND.
9
COM
Common
The common pin defines the zero reference point for all single-ended inputs. It must be
free of noise and is usually tied to the analog ground plane.
10
DGND
Digital Ground
This is the ground for the internal logic. Tie to the ground plane.
11
AGND
Analog Ground
AGND should be tied directly to the analog ground plane.
12
V
Negative Supply
Tie V to most negative potential in the circuit. (Ground in single supply applications.)
13, 14
REF , REF +
Reference Inputs
The reference inputs must be kept free of noise with respect to AGND.
15
CS
Chip Select Input
A logic low on this input enables data transfer.
16
DOUT
Digital Data Output
The A/D conversion result is shifted out of this output.
17
DIN
Data Input
The A/D configuration word is shifted into this input.
18
SCLK
Shift Clock
This clock synchronizes the serial data transfer.
19
ACLK
A/D Conversion Clock
This clock controls the A/D conversion process.
20
VCC
Positive Supply
This supply must be kept free of noise and ripple by bypassing directly to the analog
ground plane.
W
I
DAGRA
BLOCK
RSOURCE (kΩ)
0.1
1
S&H
ACQUISITION
TIME
TO
0.1%
s)
10
110
LTC1283 G13
5
VCC = 3V
VREF = 2.5V
TA = 25°C
0V TO 2.5V INPUT STEP
+
VIN
RSOURCE
+
9
8
7
6
4
3
2
INPUT
SHIFT
REGISTER
SAMPLE-
AND-
HOLD
10-BIT
CAPACITIVE
DAC
VCC
20
ANALOG
INPUT MUX
1
2
3
4
5
6
7
8
9
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DOUT
16
SCLK
18
CONTROL
AND
TIMING
15
CS
LTC1283 BD
17
REF+
14
DGND
10
AGND
11
V
12
REF
13
COMP
OUTPUT
SHIFT
REGISTER
DIN
19
ACLK
10-BIT
SAR
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