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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | LTC1287CCN8 |
| 寤犲晢锛� | Linear Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 14/16闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC DATA ACQ SYS 12BIT 3V 8-DIP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 50 |
| 椤炲瀷锛� | 鏁�(sh霉)鎿�(j霉)閲囬泦绯荤当(t菕ng)锛圖AS锛� |
| 鍒嗚鲸鐜囷紙浣嶏級锛� | 12 b |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 30k |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶锛屽苟鑱�(li谩n) |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 闆绘簮闆诲锛� | 3V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 閫氬瓟 |
| 灏佽/澶栨锛� | 8-DIP锛�0.300"锛�7.62mm锛� |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-PDIP |
| 鍖呰锛� | 绠′欢 |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)鐣�(d膩ng)鍓嶇14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)
LTC1287
7
1287fa
TEST CIRCUITS
Voltage Waveforms for ten
U
S
A
O
PPLICATI
WU
U
I FOR ATIO
The LTC1287 is a data acquisition component which
contains the following functional blocks:
1. 12-bit successive approximation capacitive A/D
converter
2. Analog multiplexer (MUX)
3. Sample-and-hold (S/H)
4. Synchronous, half-duplex serial interface
5. Control and timing logic
DIGITAL CONSIDERATIONS
Serial Interface
The LTC1287 communicates with microprocessors and
other external circuitry via a synchronous, half-duplex,
three-wire serial interface (see Operating Sequence). The
clock (CLK) synchronizes the data transfer with each bit
being transmitted on the falling CLK edge. The LTC1287
does not require a configuration input word and has no DIN
pin. It is permanently configured to have a single differen-
tial input and to operate in unipolar mode. A falling CS
initiates data transfer. The first CLK pulse enables DOUT.
After one null bit, the A/D conversion result is output on the
DOUT line with a MSB-first sequence followed by a LSB-
first sequence. With the half duplex serial interface the
DOUT data is from the current conversion. This provides
easy interface to MSB- or LSB-first serial ports. Bringing
CS high resets the LTC1287 for the next data exchange.
Logic Levels
The logic level standards for this supply range have not
been well defined. What standards that do exist are not
universally accepted. The trip point on the logic inputs of
the LTC1287 is 0.28
脳 VCC. This makes the logic inputs
compatible with HC-type levels and processors that are
DOUT
0.6V
ten
B11
CS
CLK
LTC1287 TC07
CLK
tCYC
CS
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
tCONV
DOUT
Hi-Z
tSMPL
LTC1287 F01
Figure 1. LTC1287 Operating Sequence
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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