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參數資料
| 型號： | LTC1298IS8#TR |
| 廠商： | Linear Technology |
| 文件頁數： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SAMPL MCRPWR 8SOIC |
| 標準包裝： | 2,500 |
| 位數： | 12 |
| 采樣率（每秒）： | 11.1k |
| 數據接口： | MICROWIRE?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 1.8mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 2 個單端，單極 |
15
LTC1286/LTC1298
APPLICATION INFORMATION
WU
U
BOARD LAYOUT CONSIDERATIONS
Grounding and Bypassing
The LTC1286/LTC1298 are easy to use if some care is
taken. They should be used with an analog ground plane
and single point grounding techniques. The GND pin
should be tied directly to the ground plane.
The VCC pin should be bypassed to the ground plane with
a 10
F tantalum capacitor with leads as short as possible.
If the power supply is clean, the LTC1286/LTC1298 can
also operate with smaller 1
F or less surface mount or
ceramic bypass capacitors. All analog inputs should be
referenced directly to the single point ground. Digital
inputs and outputs should be shielded from and/or routed
away from the reference and analog circuitry.
SAMPLE-AND-HOLD
Both the LTC1286 and the LTC1298 provide a built-in
sample-and-hold (S&H) function to acquire signals. The
S&H of the LTC1286 acquires input signals from “+” input
relative to “–” input during the tSMPL time (see Figure 1).
However, the S&H of the LTC1298 can sample input
signals in the single-ended mode or in the differential
inputs during the tSMPL time (see Figure 7).
Single-Ended Inputs
The sample-and-hold of the LTC1298 allows conversion
of rapidly varying signals. The input voltage is sampled
during the tSMPL time as shown in Figure 7. The sampling
interval begins as the bit preceding the MSBF bit is shifted
in and continues until the falling CLK edge after the MSBF
bit is received. On this falling edge, the S&H goes into hold
mode and the conversion begins.
Figure 7. LTC1298 “+” and “–” Input Settling Windows
CLK
DIN
DOUT
"+" INPUT
"–" INPUT
SAMPLE
HOLD
"+" INPUT MUST
SETTLE DURING
THIS TIME
tSMPL
tCONV
CS
SGL/DIFF
START
MSBF
DON'T CARE
1ST BIT TEST "–" INPUT MUST
SETTLE DURING THIS TIME
B11
LTC1096/8 F07
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