參數(shù)資料
型號: LTC1401CS8
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: Complete SO-8, 12-Bit, 200ksps ADC with Shutdown
中文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝: 0.150 INCH, PLASTIC, SOP-8
文件頁數(shù): 11/20頁
文件大?。?/td> 352K
代理商: LTC1401CS8
11
LTC1401
APPLICATIO
S I
N
FOR
ATIO
U
W
U
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1401, a printed circuit board is
required. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital traces alongside an analog signal trace
or underneath the ADC. The analog input should be
screened by GND.
High quality tantalum and ceramic bypass capacitors
should be used at the V
CC
and V
REF
pins as shown in the
Typical Application on the first page of this datasheet. For
LTC1401 F09b
+
R2
10k
R9
20
R4
100k
R5
4.3k
FULL-SCALE
ADJUST
R3
100k
R6
400
R1
10k
10k
ANALOG
INPUT
0V TO 2.048V
A1
3V
R8
10k
OFFSET
ADJUST
R7
100k
3V
A
IN
LTC1401
optimum performance, a 10
μ
F surface mount AVX capaci-
tor in parallel with a 0.1
μ
F ceramic is recommended for the
V
CC
and V
REF
pins. The capacitors must be located as close
to the pins as possible. The traces connecting the pins and
the bypass capacitors must be kept short and should be
made as wide as possible.
Input signal leads to A
IN
and signal return leads from GND
(Pin 4) should be kept as short as possible to minimize
noise coupling. In applications where this is not possible,
a shielded cable between the analog input signal and the
ADC is recommended. Also, any potential difference in
grounds between the analog signal and the ADC appears
as an error voltage in series with the analog input signal.
Attention should be paid to reducing the ground circuit
impedance as much as possible.
Figure 10 shows the recommended system ground con-
nections. All analog circuitry grounds should be termi-
nated at the LTC1401 GND pin. The ground return to the
power supply from Pin 4 should be low impedance for
noise free operation. Digital circuitry grounds must be
connected to the digital supply common.
Figure 9a. LTC1401 Full-Scale Adjust Circuit
LTC1401 F09a
+
R2
10k
R3
10k
R1
50
R4
100
FULL-SCALE
ADJUST
V
IN
A1
LTC1401
A
IN
GND
ADDITIONAL PINS OMITTED FOR CLARITY
±
20LSB TRIM RANGE
Figure 9b. LTC1401 Offset and Full-Scale Adjust Circuit
Figure 10. Power Supply Connection
ANALOG SUPPLY
GND
3V
+
LTC1401
V
CC
GND
DIGITAL SUPPLY
GND
3V
+
DIGITAL CIRCUITRY
V
CC
GND
LTC1401 F10
Power-Down Mode
Upon power up, the LTC1401 is initialized to the active
state and is ready for conversion. However, the chip can be
easily placed into Nap or Sleep mode by exercising the
right combination of CLK and CONV signals. In Nap mode,
all power is off except the internal reference which remains
active and provides 1.20V output voltage to the other
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