參數(shù)資料
型號(hào)： LTC1401CS8
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： Complete SO-8, 12-Bit, 200ksps ADC with Shutdown
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： 0.150 INCH, PLASTIC, SOP-8
文件頁數(shù)： 15/20頁
文件大?。?/td> 352K
代理商： LTC1401CS8
15
LTC1401
TYPICAL APPLICATIO
N
S
TMS320C50 Code for Circuit
THIS PROGRAM DEMONSTRATES THE LTC1401 INTERFACE TO THE
TMS320C50. FRAME SYNC PULSE IS GENERATED FROM TFSX.
DATA SHIFT CLOCK IS DERIVED FROM CLKOUT.
*Initialization*
.mmregs
;- - Initialized data memory to zero
.ds
0F00h
DATA0
.word
0
DATA1
.word
0
DATA2
.word
0
DATA3
.word
0
DATA4
.word
0
DATA5
.word
0
;- - Set up the ISR vector
.ps
080Ah
rint :
B
RECEIVE
xint :
B
TRANSMIT
trnt :
B
TREC
txnt :
B
TTRANX
;- - Setup the reset vector
.ps 0A00h
.entry
START:
*TMS320C50 Initialization*
SETC INTM
; Temporarily disable all interrupts
LDP
#0
; Set data page pointer to zero
OPL
#0834h, PMST ; Set up the PMST status and control register
LACC #0
SAMMCWSR
; Set software wait state to 0
SAMMPDWSR
;
*Configure Serial Port*
SPLK #0028h, TSPC
; Set TDM Serial Port
; TDM = 0 Stand Alone mode
; DLB = 0 Not loop back
; FO = 0 16 Bits
; FSM = 1 Burst Mode
; MCM = 0 CLKR is generated externally
; TXM = 1 FSX as output pin
; Put serial port into reset
; (XRST = RRST = 0)
SPLK #00E8h, TSPC
; Take Serial Port out of reset
; (XRST = RRST = 1)
SPLK #0FFFFh, IFR
; Clear all the pending interrupts
; Defines global symbolic names
; Initialize data to zero
; Begin sample data location
; .
; Location of data
; .
; .
; End sample data location
; Serial ports interrupts
; 0A;
; 0C;
; 0E;
; 10;
*Start Serial Communication*
SACL TDXR
SPLK #040h, IMR
CLRC INTM
CLRC SXM
; Generate frame sync pulse
; Turn on TRNT receiver interrupt
; Enable interrupt
; For Unipolar input, set for right shift
; with no sign extension
; Load the auxiliary register pointer with seven
; Load the auxiliary register seven with #0F00h
; as the begin address for data storage
; Wait for a receive interrupt
;
;
; !! Regenerate the frame sync pulse
;
MAR *AR7
LAR
AR7, #0F00h
WAIT:
NOP
NOP
NOP
SACL TDXR
B
; - - - - - - - end of main program - - - - - - - - - - ;
*Receiver Interrupt Service Routine*
TREC:
LAMMTRCV
SFR
SFR
AND
#1FFFh, 0
WAIT
; Load the data received from LTC1401
; Shift right two times
;
; ANDed with #1FFFh
; For converting the data to right
; justified format
;
; Write to data memory pointed by AR7 and
; Increase the memory address by one
;
; Compare to end sample address #0F05h
SACL *+, 0
LACC AR7
SUB
BCND
END_TRCV, GEQ
; If the end sample address has exceeded jump
to END_TRCV
;
SPLK #040h, IMR
; Else re-enable the TRNT receive interrupt
RETE
; Return to main program and enable interrupt
*After Obtained the Data from LTC1401, Program Jump to END_TRCV*
END_TRCV:
SPLK #002h, IMR
; Enable INT2 for program to halt
CLRC INTM
SUCCESS:
B
SUCCESS
*Fill the unused interrupt with RETE, to avoid program get “l(fā)ost”*
TTRANX:
RETE
RECEIVE:
RETE
TRANSMIT:
RETE
INT2:
B halt
; Halts the running CPU
#0F05h,0
相關(guān)PDF資料
PDF描述
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LTC1402C Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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