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參數(shù)資料
| 型號： | LTC1403 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Serial 12-Bit/14-Bit, 2.8Msps Sampling ADCs with Shutdown |
| 中文描述： | 串行12-Bit/14-Bit，2.8Msps采樣ADC，帶有關(guān)斷 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 323K |
| 代理商： | LTC1403 |
1
LTC1403/LTC1403A
1403af
APPLICATIU
FEATURES
DESCRIPTIO
U
BLOCK DIAGRA
W
Serial 12-Bit/14-Bit, 2.8Msps
Sampling ADCs with Shutdown
I
2.8Msps Conversion Rate
I
Low Power Dissipation: 14mW
I
3V Single Supply Operation
I
2.5V Internal Bandgap Reference can be Overdriven
I
3-Wire Serial Interface
I
Sleep (10
μ
W) Shutdown Mode
I
Nap (3mW) Shutdown Mode
I
80dB Common Mode Rejection
I
0V to 2.5V Unipolar Input Range
I
Tiny 10-Lead MS Package
, LTC and LT are registered trademarks of Linear Technology Corporation.
I
Communications
I
Data Acquisition Systems
I
Uninterrupted Power Supplies
I
Multiphase Motor Control
I
Multiplexed Data Acquisition
2nd, 3rd and SFDR
vs Input Frequency
The LTC
1403/LTC1403A are 12-bit/14-bit, 2.8Msps se-
rial ADCs with differential inputs. The devices draw only
4.7mA from a single 3V supply and come in a tiny 10-lead
MS package. A Sleep shutdown feature lowers power
consumption to 10
μ
W. The combination of speed, low
power and tiny package makes the LTC1403/LTC1403A
suitable for high speed, portable applications.
The 80dB common mode rejection allows users to elimi-
nate ground loops and common mode noise by measuring
signals differentially from the source.
The devices convert 0V to 2.5V unipolar inputs differen-
tially. The absolute voltage swing for +A
IN
and –A
IN
extends from ground to the supply voltage.
The serial interface sends out the conversion results
during the 16 clock cycles following CONV
↑
for compat-
ibility with standard serial interfaces. If two additional
clock cycles for acquisition time are allowed after the data
stream in between conversions, the full sampling rate of
2.8Msps can be achieved with a 50.4MHz clock.
–
+
1
2
7
3
4
S & H
GND
EXPOSED PAD
LTC1403A
V
REF
10
μ
F
A
IN–
A
IN+
14-BIT ADC
3V
10
μ
F
14
1
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
2.5V
REFERENCE
TIMING
LOGIC
V
DD
SDO
CONV
SCK
1403A TA01
5
6
11
FREQUENCY (MHz)
0.1
–80
T
–74
–68
–62
–56
1
10
100
1403A TA02
–86
–92
–98
–104
–50
–44
THD
3rd
2nd, SFDR
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