參數(shù)資料
型號: LTC1403AIMSE-1#TRPBF
廠商: Linear Technology
文件頁數(shù): 17/22頁
文件大小: 0K
描述: IC ADC 14BIT 2.8MSPS DIFF 10MSOP
標準包裝: 2,500
位數(shù): 14
采樣率(每秒): 2.8M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 12mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 10-MSOP 裸露焊盤
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;1 個差分,單極
配用: DC1082A-D-ND - BOARD SAR ADC LTC1403A
DC1082A-C-ND - BOARD SAR ADC LTC1403A-1
LTC1403-1/LTC1403A-1
4
14031fc
TIMING CHARACTERISTICS
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIH
High Level Input Voltage
VDD = 3.3V
l
2.4
V
VIL
Low Level Input Voltage
VDD = 2.7V
l
0.6
V
IIN
Digital Input Current
VIN = 0V to VDD
l
±10
A
CIN
Digital Input Capacitance
(Note 20)
5
pF
VOH
High Level Output Voltage
VDD = 3V, IOUT = –200A
l
2.5
2.9
V
VOL
Low Level Output Voltage
VDD = 2.7V, IOUT = 160A
VDD = 2.7V, IOUT = 1.6mA
l
0.05
0.10
0.4
V
IOZ
Hi-Z Output Leakage DOUT
VOUT = 0V to VDD
l
±10
A
COZ
Hi-Z Output Capacitance DOUT
1
pF
ISOURCE
Output Short-Circuit Source Current
VOUT = 0V, VDD = 3V
20
mA
ISINK
Output Short-Circuit Sink Current
VOUT = VDD = 3V
15
mA
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 17)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Supply Voltage
2.7
3.6
V
IDD
Positive Supply Voltage
Active Mode
Nap Mode
Sleep Mode (LTC1403-1)
Sleep Mode (LTC1403A-1)
l
4.7
1.1
2
7
1.5
15
10
mA
A
PD
Power Dissipation
Active Mode with SCK in Fixed State (Hi or Lo)
12
mW
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VDD = 3V
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX) Maximum Sampling Frequency per Channel
(Conversion Rate)
l
2.8
MHz
tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period)
l
357
ns
tSCK
Clock Period
(Note 16)
l
19.8
10000
ns
tCONV
Conversion Time
(Note 6)
16
18
SCLK cycles
t1
Minimum Positive or Negative SCLK Pulse Width
(Note 6)
2
ns
t2
CONV to SCK Setup Time
(Notes 6, 10)
3
ns
t3
Nearest SCK Edge Before CONV
(Note 6)
0
ns
t4
Minimum Positive or Negative CONV Pulse Width
(Note 6)
4
ns
t5
SCK to Sample Mode
(Note 6)
4
ns
t6
CONV to Hold Mode
(Notes 6, 11)
1.2
ns
t7
16th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
(Notes 6, 7, 13)
45
ns
t8
Minimum Delay from SCKto Valid Data
(Notes 6, 12)
8
ns
t9
SCK to Hi-Z at SDO
(Notes 6, 12)
6
ns
t10
Previous SDO Bit Remains Valid After SCK
(Notes 6, 12)
2
ns
t12
VREF Settling Time After Sleep-to-Wake Transition
(Notes 6, 14)
2
ms
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V
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