參數(shù)資料
型號: LTC1403AIMSE-1#TRPBF
廠商: Linear Technology
文件頁數(shù): 6/22頁
文件大小: 0K
描述: IC ADC 14BIT 2.8MSPS DIFF 10MSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 14
采樣率(每秒): 2.8M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 12mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 10-MSOP 裸露焊盤
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,單極;1 個差分,單極
配用: DC1082A-D-ND - BOARD SAR ADC LTC1403A
DC1082A-C-ND - BOARD SAR ADC LTC1403A-1
LTC1403-1/LTC1403A-1
14
14031fc
APPLICATIONS INFORMATION
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1403-1/LTC1403A-1, a printed
circuit board with ground plane is required. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
track alongside an analog signal track. If optimum phase
match between the inputs is desired, the length of the two
input wires should be kept matched.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in the
Block Diagram on the first page of this data sheet. For op-
timum performance, a 10F surface mount AVX capacitor
with a 0.1F ceramic is recommended for the VDDandVREF
pins. Alternatively, 10F ceramic chip capacitors such as
Murata GRM219R60J106M may be used. The capacitors
mustbelocatedasclosetothepinsaspossible.Thetraces
connecting the pins and the bypass capacitors must be
kept short and should be made as wide as possible.
Figure7showstherecommendedsystemgroundconnec-
tions. All analog circuitry grounds should be terminated at
the LTC1403-1/LTC1403A-1 GND (Pins 4, 5, 6 and exposed
pad). The ground return from the LTC1403-1/LTC1403A-1
(Pins 4, 5, 6 and exposed pad) to the power supply
should be low impedance for noise free operation. Digital
circuitry grounds must be connected to the digital supply
common. In applications where the ADC data outputs and
control signals are connected to a continuously active
microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
from the microprocessor to the successive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus.
POWER-DOWN MODES
Upon power-up, the LTC1403-1/LTC1403A-1 is initialized
to the active state and is ready for conversion. The Nap
and Sleep mode waveforms show the power-down modes
for the LTC1403-1/LTC1403A-1. The SCK and CONV inputs
control the power-down modes (see Timing Diagrams).
Two rising edges at CONV, without any intervening ris-
ing edges at SCK, put the LTC1403-1/LTC1403A-1 in Nap
mode and the power drain drops from 14mW to 6mW.
The internal reference remains powered in Nap mode.
Figure 7. Recommended Layout
14031 F07
FREQUENCY (Hz)
MAGNITUDE
(dB)
–60
–30
–20
14031 F06b
–70
–80
–120
–100
0
–10
–40
–50
–90
–110
0
371k
185k
556k
741k
Figure 6b. LTC1403-1 6MHz Sine Wave 4096 Point FFT Plot
with the LT1819 Driving the Inputs Differentially
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