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參數(shù)資料
| 型號(hào)： | LTC1410IG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | ADC |
| 英文描述： | 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown |
| 中文描述： | 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-28 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 148K |
| 代理商： | LTC1410IG |
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4
LTC 1410
POWER REQUIRW U
otherwise specifications are at T
A
= 25
°
C. (Note 5)
SYMBOL
PARAMETER
P
D
Power Dissipation
Nap Mode
Sleep Mode
The
G
denotes specifications which apply over the full operating temperature range,
CONDITIONS
MIN
TYP
160
7.5
0.01
MAX
230
12
1
UNITS
mW
mW
mW
SHDN = 0V, NAP/SLP = 5V
SHDN = 0V, NAP/SLP = 0V
SYMBOL
f
SAMPLE(MAX)
t
CONV
t
ACQ
t
ACQ+CONV
PARAMETER
Maximum Sampling Frequency
Conversion Time
Acquisition Time
Throughput Time
(Acquisition + Conversion)
CS to RD Setup Time
CS
↓
to CONVST
↓
Setup Time
NAP/SLP
↓
to SHDN
↓
Setup Time
SHDN
↑
to CONVST
↓
Wake-Up Time (Note 10)
CONVST
Low Time
CONVST to BUSY Delay
CONDITIONS
MIN
1.25
TYP
MAX
UNITS
MHz
G
G
650
50
750
100
800
ns
ns
ns
G
G
t
1
t
2
t
3
t
4
t
5
t
6
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
G
0
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
G
G
200
(Notes 10, 11)
C
L
= 25pF
G
40
10
G
50
t
7
Data Ready Before BUSY
↑
20
15
40
–5
35
G
t
8
t
9
t
10
Delay Between Conversions
Wait Time RD
↓
After BUSY
↑
Data Access Time After RD
↓
(Note 10)
(Note 10)
C
L
= 25pF
G
G
15
25
35
35
50
20
25
30
G
C
L
= 100pF
20
G
t
11
Bus Relinquish Time
8
Commercial
Industrial
G
G
t
12
t
13
t
14
RD Low Time
CONVST High Time
Aperture Delay of Sample-and-Hold
G
t
10
40
G
–1.5
TW U
range, otherwise specifications are at T
A
= 25
°
C. (Note 5)
The
G
denotes specifications which apply over the full operating temperature
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8:
Bipolar offset is the offset voltage measured from –0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9:
Guaranteed by design, not subject to test.
Note 10:
Recommended operating conditions.
Note 11:
The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 425ns after the
start of the conversion or after BUSY rises.
Note 12:
Signal-to-noise ratio (SNR) is measured at 100kHz and distortion
is measured at 600kHz. These results are used to calculate signal-to-noise
plus distortion (SINAD).
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with DGND, OGND
and AGND wired together unless otherwise noted.
Note 3:
When these pin voltages are taken below V
SS
or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below V
SS
or above V
DD
without latchup.
Note 4:
When these pin voltages are taken below V
SS
, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below V
SS
without latchup. These pins are not clamped to V
DD
.
Note 5:
V
DD
= 5V, V
SS
= –5V, f
SAMPLE
= 1.25MHz, t
r
= t
f
= 5ns unless
otherwise specified.
Note 6:
Linearity, offset and full-scale specifications apply for a single-
ended +A
IN
input with –A
IN
grounded.
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