參數(shù)資料
型號: LTC1410IG
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown
中文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28
封裝: 0.209 INCH, PLASTIC, SSOP-28
文件頁數(shù): 7/16頁
文件大小: 148K
代理商: LTC1410IG
7
LTC 1410
TEST CIRCUITS
APPLICATIO
S I
FOR
ATIO
U
W
U
U
CONVERSION DETAILS
The LTC1410 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the +A
IN
and –A
IN
inputs are
connected to the sample-and-hold capacitors (C
SAMPLE
)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum duration of 100ns will provide enough time for
the sample-and-hold capacitors to acquire the analog
signal. During the convert phase the comparator zeroing
switches open, putting the comparator into compare
mode. The input switches connect the C
SAMPLE
capacitors
to ground, transferring the differential analog input charge
1k
C
L
C
L
DBN
(A) Hi-Z TO V
OH
AND V
OL
TO V
OH
(B) Hi-Z TO V
OL
AND V
OH
TO V
OL
DBN
1k
5V
1410 TC01
1k
100pF
100pF
DBN
(A) V
OH
TO Hi-Z
(B) V
OL
TO Hi-Z
DBN
1k
5V
1410 TC02
Load Circuits for Access Timing
Load Circuits for Output Float Delay
onto the summing junctions. This input charge is succes-
sively compared with the binarily-weighted charges sup-
plied by the differential capacitive DAC. Bit decisions are
made by the high speed comparator. At the end of a
conversion, the differential DAC output balances the +A
IN
and –A
IN
input charges. The SAR contents (a 12-bit data
word) which represent the difference of +A
IN
and –A
IN
are
loaded into the 12-bit output latches.
SAMPLE
HOLD
+C
SAMPLE
–C
SAMPLE
D11
D0
ZEROING SWITCHES
+A
IN
+C
DAC
+V
DAC
–C
DAC
–V
DAC
–A
IN
12
1410 F01
COMP
+
OUTPUT
LATCHES
SAR
SAMPLE
HOLD
HOLD
HOLD
Figure 1. Simplified Block Diagram
相關PDF資料
PDF描述
LTC1410CG 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown
LTC1410 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown
LTC1410C 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown
LTC1410CSW 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown
LTC1410I 12-Bit, 1.25Msps Sampling A/D Converter with Shutdown
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