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參數(shù)資料
| 型號： | LTC1416CG |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC A/D CONV 14BIT SAMPLNG 28SSOP |
| 標準包裝： | 47 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 400k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，雙極 |
18
LTC1416
APPLICATIONS INFORMATION
WU
U
Shutdown is controlled by Pin 21 (SHDN), the ADC is in
shutdown when it is low. The shutdown mode is selected
with Pin 20 (CS), low selects nap.
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CONVST, CS and RD. A logic “0”
applied to the CONVST pin will start a conversion after the
ADC has been selected (i.e., CS is low). Once initiated, it
cannot be restarted until the conversion is complete.
Converter status is indicated by the BUSY output. BUSY is
low during a conversion.
Figures 16 through 21 show several different modes of
operation. In modes 1a and 1b (Figures 17 and 18), CS and
RD are both tied low. The falling edge of CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 19), CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared MPU data
bus.
In slow memory and ROM modes (Figures 20 and 21), CS
is tied low and CONVST and RD are tied together. The MPU
Figure 16. CS to CONVST Setup Timing
t2
t1
CS
CONVST
RD
1416 F16
DATA N
DB13 TO DB0
DATA (N + 1)
DB13 TO DB0
DATA (N – 1)
DB13 TO DB0
CONVST
CS = RD = 0
BUSY
1416 F17
t5
tCONV
t6
t8
t7
DATA
(SAMPLE N)
(CONVST =
)
Figure 17. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode, the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a Wait state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high releasing the
processor, and the processor takes RD (= CONVST) back
high and reads the new conversion data.
In ROM mode, the processor takes RD (= CONVST) low,
starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.
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