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參數(shù)資料
| 型號(hào)： | LTC1421-2.5CSW |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 14-bit, 5V, 200KSPS, 4-Channel Unipolar ADC 20-SOIC 0 to 70 |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 464K |
| 代理商： | LTC1421-2.5CSW |
14
LTC1421/LTC1421-2.5
APPLICATIO
S I
N
FOR
ATIO
U
When CON1 and CON2 are both forced to ground for more
than 20ms, the LTC1421 assumes that the board is fully
connected to the host and power-up can begin. When
V
CCLO
and V
CCHI
exceed the 2.45V undervoltage lockout
threshold, the 20
μ
A current reference is connected from
RAMP to GND, the charge pumps are turned on and CPON
is forced high (time point 4). V
OUTHI
and V
OUTLO
begin to
ramp up. When V
OUTLO
exceeds the reset threshold volt-
age, PWRGD will immediately be forced high (time point
5). After a 200ms delay, RESET will be pulled high and
DISABLE will be pulled low, enabling the data bus (time
point 6).
W
U
Ground Sense Comparator
When POR is pulled low for more than 20ms, GATELO and
GATEHI are pulled to ground and V
OUTLO
and V
OUTHI
will
be discharged. If POR is pulled back high while V
OUTLO
and V
OUTHI
are still ramping down, the discharge will
continue. When they drop below the V
TRIP
point, a power-
up sequence will begin automatically. The trip point poten-
tial for LTC1421 is set at 0.1V and 2.5V for LTC1421-2.5.
In applications, where either V
OUTLO
or V
OUTHI
might be
forced above 100mV before power-up, the LTC1421-2.5
should be used. This could occur when leakage through
the body diode of the logic chips keeps V
OUTLO
high or in
the case where logic lines are precharged.
In other applications, where outputs need to drop to near
ground potential before ramping up again to ensure proper
initial state for the logic chips, the LTC1421 should be
used.
Power-On Reset Timing
The POR input is used to completely cycle the power
supplies on the board or to reset the electronic circuit
breaker feature. The POR pin can be connected to a
grounded push button, toggle switch or a logic signal
from the host. When POR is pulled low for more than
20ms, a power-on reset sequence begins (Figure 15,
Figure 15. Power-On Reset Timing
V
CCHI
V
CCLO
1
2
3
4
5
6
7
DISABLE
FAULT
POR
CON1
CON2
V
OUTLO
V
OUTHI
CPON
V
TH2
1421 F15
V
TH1
20ms
200ms
32
μ
s
GATEHI
GATELO
RESET
PWRGD
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