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參數(shù)資料
| 型號： | LTC1421-2.5CSW |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 14-bit, 5V, 200KSPS, 4-Channel Unipolar ADC 20-SOIC 0 to 70 |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 464K |
| 代理商： | LTC1421-2.5CSW |
15
LTC1421/LTC1421-2.5
APPLICATIO
S I
N
FOR
ATIO
U
time point 2). Pulses less than 20ms on POR are ignored.
CPON goes low. Both GATEHI and GATELO will be
actively pulled down to GND
. When V
OUTLO
drops below
its reset threshold voltage, PWRGD will immediately pull
low (time point 3) followed by RESET and DISABLE 32
μ
s
later (time point 4). Both supplies will be discharged to
ground and stay there until POR is pulled high.
The circuit breaker can be reset by pulling POR low. After
POR is low for more than 20ms, the chip will immediately
try to power up the supplies.
W
U
Circuit Breaker Timing
The waveforms for the circuit when a short occurs on
either supply during board insertion are shown in
Figure 16. Time points 1 to 4 are the same as the board
insertion example, but at time point 5, a short circuit is
detected on one of the supplies. The charge pumps are
immediately turned off, the outputs V
OUTHI
and V
OUTLO
are
actively pulled to GND and the CPON and FAULT pins are
pulled low. At time point 6, the circuit breaker is reset by
pulling POR low. After POR has been low for 20ms (time
point 7), CPON and FAULT are pulled high, the 20
μ
A
reference current is connected to RAMP and the charge
pumps are enabled. V
OUTHI
and V
OUTLO
ramp up at a
controlled rate. When V
OUTLO
has exceeded its reset
threshold, the PWRGD signal is pulled high (time point 8).
After a 200ms delay, RESET is pulled high and DISABLE
goes low.
Figure 16. Circuit Breaker Timing
V
CCLO
1
2
3
4
5
6
V
CCHI
DISABLE
CON1
7
8
9
CON2
CPON
PWRGD
V
TH1
1421 F16
V
OUTHI
GATEHI
GATELO
V
OUTLO
RESET
FAULT
POR
20ms
20ms
200ms
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