參數資料
| 型號： | LTC1456IN8#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 7/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC D/A CONV 12BIT R-R 8-DIP |
| 標準包裝： | 50 |
| 設置時間： | 14µs |
| 位數： | 12 |
| 數據接口： | 串行 |
| 轉換器數目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.2mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應商設備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 輸出數目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
7
LTC1456
OPERATIO
U
and CS/LD signals remain common to all chips in the daisy
chain. The serial data is clocked to all of the chips, then the
CS/LD signal is pulled high to update all of them simulta-
neously.
Voltage Output
The LTC1456's rail-to-rail buffered output can source or
sink 5mA over the entire operating temperature range
while pulling to within 300mV of the positive supply
voltage or ground. The output swings to within a few
millivolts of either supply rail when unloaded and has an
equivalent output resistance of 40
when driving a load to
the rails. The output can drive 1000pF without going into
oscillation.
Serial Interface
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/LD is pulled high. The CLK is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse.
When CLR is pulled low it asynchronously resets the shift
and DAC registers to all zeros.
The buffered output of the 12-bit shift register is available
on the DOUT pin which swings from GND to VCC. Multiple
LTC1456s may be daisy-chained together by connecting
the DOUT pin to the DIN pin of the next chip, while the CLK
CLR
CLK
DIN
CS/LD
P
0.1
F
VCC
VOUT
GND
5V
LTC1456
1456 TA04
–
+
LT1077
VS + 5V TO 100V
FOR RL ≤ 50
Q1
2N3440
RA
410
RL
IOUT =
≈ 0mA TO 10mA
DIN 4.095
4096 RA
TYPICAL APPLICATION
U
The circuit below shows a digitally programmable current
source from an external voltage source using an external
op amp, an LT
1077 and an NPN transistor (2N3440). Any
digital word from 0 to 4095 is loaded into the LTC1456 and
its output correspondingly swings from 0V to 4.095V. In
the configuration shown, this voltage will be forced across
the resistor RA. If RA is chosen to be 410 the output
current will range from 0mA at zero scale to 10mA at full
scale. The minimum voltage for VS is determined by the
load resistor RL and Q1’s VCESAT voltage. With a load
resistor of 50
, the voltage source can be as low as 5V.
12-Bit 5V Single Supply Voltage Output DAC
DIN
CLK
CS/LD
DOUT
P
0.1
F
OUTPUT
0V TO 4.095V
VCC
VOUT
GND
LTC1456
CLR
TO NEXT DAC FOR
DAISY-CHAINING
4.5V TO 5.5V
1456 TA03
Digitally Programmable Current Source
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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