參數(shù)資料
型號: NB6L16DTR2G
廠商: ON Semiconductor
文件頁數(shù): 1/12頁
文件大?。?/td> 0K
描述: IC CLK BUFF DRIVER XLATOR 8TSSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 緩沖器/驅(qū)動(dòng)器,變換器
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
輸入: CML,LVCMOS,LVDS,LVNECL,LVPECL,LVTTL
輸出: ECL
頻率 - 最大: 6GHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2008
December, 2008 Rev. 8
1
Publication Order Number:
NB6L16/D
NB6L16
2.5V / 3.3V Multilevel Input to
Differential LVPECL/LVNECL
Clock or Data Receiver/
Driver/Translator Buffer
The NB6L16 is a high precision, low power ECL differential clock
or data receiver/driver/translator buffer. The device is functionally
equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With
output transition times of 70 ps, it is ideally suited for high frequency,
low power systems. The device is targeted for Backplane buffering,
GbE clock/data distribution, Fibre Channel distribution and SONET
clock/data distribution applications.
Input accept LVNECL (Negative ECL), LVPECL (Positive ECL),
LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV
ECL signals.
The VBB pin, an internally generated voltage supply, is available to
this device only. For singleended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Features
Input Clock Frequency w 6 GHz
Input Data Rate Frequency w 6 Gb/s
Low 12 mA Typical Power Supply Current
70 ps Typical Rise/Fall Times
130 ps Input Propagation Delay
OnChip Reference for ECL SingleEnded Input VBB Output
PECL Mode Operating Range:
VCC = 2.375 V to 3.465 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 2.375 V to 3.465 V
Open Input Default State
LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input
Compatible
PbFree Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
MARKING
DIAGRAMS*
6L16
ALYWG
G
SOIC8
D SUFFIX
CASE 751
1
8
TSSOP8
DT SUFFIX
CASE 948R
1
8
1
8
*For additional marking information, refer to
Application Note AND8002/D.
1
8
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
6L16
ALYW
G
(Note: Microdot may be in either location)
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