參數(shù)資料
型號(hào): LTC1553LCSW
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor
中文描述: SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PDSO20
封裝: 0.300 INCH, PLASTIC, SO-20
文件頁數(shù): 13/20頁
文件大?。?/td> 370K
代理商: LTC1553LCSW
13
LTC1553L
APPLICATIO
S I
FOR
ATIO
U
W
U
U
R
P
( )
DC Q
[
I
V
(
P
V
I
R
P
( )
DC Q
[
I
V
P
V
V
I
DS ON Q
MAX Q
]
(
MAX
IN
MAX Q
)(
OUT
( )
MAX
DS ON Q
MAX Q
MAX
IN
MAX Q
)(
IN
OUT
MAX
]
(
=
)
=
( )
)
=
)
=
(
)
1
1
2
1
2
2
2
2
2
2
1
2
P
MAX
should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
efficiency circuit designed for Pentium II with a 5V input
and a 2.8V, 11.2A output might allow no more than 4%
efficiency loss at full load for each MOSFET. Assuming
roughly 90% efficiency at this current level, this gives a
P
MAX
value of:
[(2.8)(11.2A/0.9)(0.04)] = 1.39W per FET
and a required R
DS(ON)
of:
=
( )(
(
( )(
(
R
V
W
V
A
R
V
W
V
V
A
DS ON Q
DS ON Q
)
)
)(
5
=
=
)
)(
)
=
1
2
2
2
5
1 39
2 8
11 2
0 019
1 39
5
2 8
11 2
0 025
Note also that while the required R
DS(ON)
values suggest
large MOSFETs, the dissipation numbers are only 1.39W
per device or less––large TO-220 packages and heat sinks
are not necessarily required in high efficiency applica-
tions. Siliconix Si4410DY or International Rectifier IRF7413
(both in SO-8) or Siliconix SUD50N03 or Motorola
MTD20N03HDL (both in D PAK) are small footprint sur-
face mount devices with R
DS(ON)
values below 0.03
at 5V
of gate drive that work well in LTC1553L circuits. With
higher output voltages, the R
DS(ON)
of Q1 may need to be
significantly lower than that for Q2. These conditions can
often be met by paralleling two MOSFETs for Q1 and using
a single device for Q2. Note that using a higher P
MAX
value
in the R
DS(ON)
calculations will generally decrease MOSFET
cost and circuit efficiency while increasing MOSFET heat
sink requirements.
Q1
G1
20
Q2
0.1
μ
F
L
O
V
OUT
1553L F07
C
OUT
C
IN
V
IN
PV
CC
1N5243B
13V
1N5817
OPTIONAL FOR V
IN
> 5V
G2
1
LTC1553L
2
+
+
Figure 7. Doubling Charge Pump
If the OUTEN pin is low, G1 and G2 are both held low to
prevent output voltage undershoot. As V
CC
and PV
CC
power up from a 0V condition, an internal undervoltage
lockup circuit prevents G1 and G2 from going high until
V
CC
reaches about 3.5V. If V
CC
powers up while PV
CC
is at
ground potential, the SS is forced to ground potential
internally. SS clamps the COMP pin low and prevents the
drivers from turning on. On power-up or recovery from
thermal shutdown, the drivers are designed such that G2
is held low until G1 first goes high.
Power MOSFETs
Two N-channel power MOSFETs are required for most
LTC1553L circuits. Logic level MOSFETs should be used
and they should be selected based on on-resistance con-
siderations. R
DS(ON)
should be chosen based on input and
output voltage, allowable power dissipation and maxi-
mum required output current. In a typical LTC1553L buck
converter circuit the average inductor current is equal to
the output load current. This current is always flowing
through either Q1 or Q2 with the power dissipation split up
according to the duty cycle:
( )
=
(
DC Q
V
V
DC Q
V
V
V
V
V
OUT
IN
OUT
IN
IN
OUT
IN
1
2
1
( )
=
=
)
The R
DS(ON)
required for a given conduction loss can now
be calculated by rearranging the relation P = I
2
R.
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